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83 results about "Digital filter design" patented technology

System for digital filtering in a fixed number of clock cycles

An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad. A RAM is used to store the state variables for the 2nd order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and/or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional modules of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional modules.
Owner:WSOU INVESTMENTS LLC +1

Recursive digital filter with reset

An integrated circuit, e.g. an Audio Codec (AC) '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a direct current (DC) buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad. A random access memory (RAM) is used to store the state variables for the 2nd order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and/or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional blocks of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional blocks.
Owner:LUCENT TECH INC +1

Distributed gain for audio codec

An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and / or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad. A RAM is used to store the state variables for the 2nd order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and / or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional blocks of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional blocks.
Owner:LUCENT TECH INC

Design method of high-order limited impulse response digital filter

The invention relates to a method for designing a high-order finite impulse response digital filter, which comprises the following steps that: a neural network method is utilized and the amplitude-frequency response error sum of squares of a filter to be designed and an ideal filter serves as the calculation energy function of a neural network; the gradient descent learning algorithm is adopted to train the weight of the neural network to minimize the amplitude-frequency response error sum of squares of the filter to be designed and the ideal filter; when the neural network is stabilized, each parameter of the finite impulse response digital filter can be obtained and then the design of the finite impulse response digital filter is completed. The high-order finite impulse response digital filter designed by the method of the invention is characterized by small pass band fluctuation, large stop-band attenuation, controllable boundary frequency and high precision, etc., especially by that no matrix inversion algorithm is required to be carried out in the design, thus having fast operation speed, and the filter has broad application prospect in the engineering fields such as data transmission, high-precision televisions, radar and sonar systems and voice and image processing, etc.
Owner:HUNAN UNIV

Method for designing digital filter applied in inertia device

InactiveCN102055434AImprove denoising effectSatisfactory filter performanceDigital technique networkBilinear transformUltrasound attenuation
The invention relates to a method for designing a digital filter applied in an inertia device. The method is characterized by comprising the following steps of: determining an amplitude attenuation allowable value according to the precision of the inertia device, determining a phase delay allowable value according to the performance index of a strap-down inertial navigation system, and determining certain technical parameters of the filter according to the actual signal power spectrum analysis of the inertia device; designing a reference analog filter, converting the reference analog filter into an infinite impulse response (IIR) digital filter by using a bilinear transform method, observing a bode diagram in the filter parameter adjusting process, and performing off-line simulation calculation according to the actually measured data; and performing judgment by using de-noising effect, common cutoff frequency, amplitude attenuation and phase delay as fuzzy variables and using fuzzy rules to optimize the integral performance index. The digital filter designed by using the method can effectively filter the noise in the inertia device, meanwhile, controls the amplitude attenuation and the phase delay in an allowable range, and ensures the precision of the signals.
Owner:北京华力创通科技股份有限公司

Programmable overflow protection in digital processing

An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad. A RAM is used to store the state variables for the 2nd order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and/or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional blocks of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional blocks.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE +1

One-dimensional film-cavity type unequal bandwidth optical interleaver design method

The invention relates to a one-dimensional film-cavity type unequal bandwidth optical interleaver design method at any duty ratio. The structure is formed by cascading the dielectric cavities with the multilayer films vapor-deposited on the left and right sides. The multilayer film structure between the dielectric cavities is equivalent to be a reflector to obtain a simplified structure of a multi-cavity reflector cascading structure. z transformation of a digital signal processing theory is introduced to obtain a reflection transmission function expression of the simplified structure, and on this basis, through the combination with the Butterworth digital filter design method, the optimal reflection coefficient of each reflector can be obtained by means of a genetic algorithm. At the end, the multilayer film structure between the dielectric cavities is constructed based on the optimal reflection coefficient to realize the design of the one-dimensional film-cavity type unequal bandwidth optical interleaver. The method is simple by means of the mature digital filter design method, and the designed one-dimensional film-cavity type unequal bandwidth optical interleaver is simple in structure and easy to manufacture in actual condition; and moreover, the optical interleaver at any duty ratio can be designed, and the output spectrum with high flatness characteristic can be obtained.
Owner:SHANGHAI UNIV
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