7results about "Data comparison" patented technology

A reference map generator clusters, into a semantic map, a set of data documents selected according to at least one criterion and associated with a medical diagnosis. A parser generates an enumeration of measurements occurring in the set of data documents. A representation generator generates for each measurement in the enumeration, a sparse distributed representation (SDR). The method includes storing, by a processor on a second computing device, in each of a plurality of memory cells on the second computing device, one of the generated SDRs. A diagnosis support module receives a document comprising a plurality of measurements. The representation generator generates a compound SDR for the document. Each of the plurality of bitwise comparison circuits determine a level of overlap between the compound SDR and the stored generated SDR. The diagnosis support module provides an identification of the medical diagnosis associated with a stored SDR.

The objective of the present invention is to assist work performed by an operator to confirm whether software that has been restored using a backup file has been returned to a time point in the past. A robot system 1 according to one aspect of the present disclosure comprises a robot device 20, a control device 10 for controlling the robot device, and a teaching operation panel 30 connected to the control device. The control device includes a means for storing information relating to control of the robot, and a means for generating data relating to an information screen for displaying the stored information. The teaching operation panel includes: a display means for displaying the information screen; a saving means for saving the displayed information screen as an image data file in association with a saved date and time; and a comparing means for comparing two image data files having different saved dates and times.

The present application discloses a carry logic circuit, a carry cascade circuit, and a chip. The carry logic circuit comprises Y stages of cascaded carry operation modules and a carry output module; each stage of carry operation module is used for receiving i pairs of arithmetic signals; a first-stage carry operation module is used for outputting a first-stage carry generation signal and outputting a first-stage carry propagation signal; an x th-stage carry operation module is further used for receiving a previous-stage carry generation signal and a previous-stage carry propagation signal, outputting an x th-stage carry generation signal, and outputting an x th-stage carry propagation signal; and the carry output module is used for receiving an initial carry signal, a Y th-stage carry generation signal, and a Y th-stage carry propagation signal, and outputting a first carry signal. The present application improves the carry operation performance of the carry logic circuit.

A data padding method comprises: determining a length of a space occupied by remaining data in the register; comparing the length of the space occupied; performing, when the length of the space occupied by the remaining data is less than the length of the unit input data, following operations: receiving a unit input data and storing it continuously with the remaining data in the register; determining a length of a unit output data to be output; intercepting a portion of data with a length of N words from data formed by padding the remaining data buffered in the register and the unit input data and starting from an address space of a lowest bit of the register, as the unit output data and outputting it; and shifting the data remaining in the register as a whole to an address space in the register starting from the lowest bit.

The embodiment of the invention discloses a leading zero detection circuit which comprises a first selection module, a comparison module and a second selection module, the input end of the second selection module is connected with the output end of the first selection module, and the selection end of the second selection module is connected with the output end of the comparison module; the floating point operand is equally divided into N sections of input numbers, each group of input ends of the first selection module inputs a group of preset constants, each section of input number is input into one selection end of the first selection module, and the first selection module is configured to output N leading zero data of the floating point operand in parallel; the comparison module is configured to input each segment of input number and output a preset identifier corresponding to each segment of input number in parallel; and the output end of the second selection module is configured to output the leading zero quantity according to N preset identifiers, so that segmentation parallel and result cascading are realized, the stage number of a key path can be greatly reduced, and the implementation delay of the leading zero detector is remarkably reduced.

The invention relates to the technical field of digital integrated circuits, and discloses an 8-4 stable sorting system, which comprises an odd-even descending sorting module for descending sorting of the first four bits of an input mask signal and the first four bits of a corresponding data signal; the odd-even ascending order sorting module is used for carrying out ascending order sorting on the last four bits of the input mask signals and the last four bits of the corresponding data signals; and the selection output module is used for selecting output signals of the odd-even descending sorting module and the odd-even ascending sorting module and finally outputting four-bit data. According to the invention, 8-bit data are sorted in an odd-even descending order and an odd-even ascending order for parallel processing, so that the resource consumption of a multiplexer is reduced by half; and through two times of cycle comparison of an odd-even sorting algorithm, elements with the same priority are ensured to keep an original relative sequence, and stable sorting is realized.

The present invention relates to a location code generator and methods therefor. The location code generator is configured for receiving an input of types and subtypes of locations in a warehouse, as well as inputs of particular locations to be omitted, and automatically generates location codes for each of the locations. The location code generator further automatically generates checking codes that meet the requirements of avoiding repeatability conflicts, proximity conflicts, and predictability conflicts. The location code generator automatically associates generated checking codes with the generated location codes. The location code generator is further configured for generating printed stickers of the generated location codes and associated checking codes.