FIFO module, deskew circuit and rate matching circuit having the same

Abstract

A first-in-first-out (FIFO) module is disclosed. The FIFO module includes multiple individually addressable memory locations, a write pointer, a read pointer and at least additional pointer. The writepointer is connected to the memory bank for addressing a first memory location to write a datum on an input data bus into the first memory location. The read pointer is connected to the memory bank for addressing a second memory location to read a datum stored therein onto an output data bus. The at least one additional pointer is connected to the memory bank for addressing a third memory location to read a datum stored therein. A deskew circuit and a rate matching circuit which utilize the FIFO module, and a deskew method are also disclosed.

Description

technical field [0001] The present invention relates to a FIFO module, and a delay equalization (deskew) circuit and a rate matching circuit having the FIFO module. Background technique [0002] Continued demand for higher-speed network connections has led to the development of 10 Gigabit Fiber Channel (10GFC) and 10 Gigabit Ethernet (10GbE) networks. In a 10GbE network, between the Media Access Control (MAC) layer and the Physical (PHY) layer, there is a 10 Gigabit Media Independent Interface (XGMII). XGMII provides full-duplex operation at a rate of 10Gb / s between the MAC layer and the PHY layer. Each direction of operation is independent of the other and includes 32 bits of data, along with clock and control signals to define a 74-bit interface between the MAC layer and the PHY layer. [0003] To solve the problems associated with routing such a large number of signals for a 74-bit interface over a distance of more than 7 cm, the 10 Gigabit Attachment Unit Interface (XA...

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Problems solved by technology

Therefore, delay equalization is delayed, and rate matching performed after delay equalization is also delayed

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