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A controlled shared memory smart switch system

A switch and shared buffer technology, applied in circuit switching systems, transmission systems, digital transmission systems, etc., can solve problems such as inability to receive different messages, time-consuming switch settings, non-optimal switch settings, etc.

Inactive Publication Date: 2005-08-24
INTERACTIC HLDG LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] There are some disadvantages in the message management scheme of the prior art: 1) the setting of the switch is time-consuming; 2) the setting of the switch is not optimal; 3) two output ports cannot receive different messages from the same input port at the same time

Method used

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  • A controlled shared memory smart switch system
  • A controlled shared memory smart switch system
  • A controlled shared memory smart switch system

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Embodiment Construction

[0038]In order to understand the working principle of the system 200, a deeper understanding of the working principles of the input controller, output controller, shared buffer, and switches S1 and S2 is required. It is also necessary to understand the content and format of the data of the transport packet, and the content and format of the control information of the transport packet.

[0039] Package Format and Layout Description

[0040] Packets entering the system are broken down into segments and further into fragments. These fragments pass through the system and are reassembled into segments, which in turn are reassembled into outgoing message packets. Segments are controlled from input ports to output ports through switches S1 and S2. In addition to message packets, there are a number of control packets that are passed between different locations in the system. Control packets are not passed through switches S1 and S2. Before describing the components shown in system...

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PUM

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Abstract

An interconnect structure comprising a plurality of input ports and a plurality of output ports with messages being sent from an input port to a predetermined output port through a switch S. Advantageously, the setting of switch S is not dependent upon the predetermined output port to which a particular message is being sent.

Description

[0001] Related patents and patent applications [0002] The disclosed systems and methods of work relate to subject matter disclosed in the following patents and patent applications, which are incorporated herein by reference in their entirety: [0003] 1. US Patent No. 5996020 entitled "Multi-level Minimal Logic Network" by Coke S. Reed as the inventor. [0004] 2. The inventor is John Hesse's US Patent No. 6289021 entitled "Scalable Low Latency Switch for Use in Interconnect Fabrics". [0005] 3. US Patent Application Serial No. 09 / 693359 entitled "Multi-Way Wormhole Interconnection" whose inventor is John Hesse. [0006] 4. US Patent Application Serial No. 09 / 693357 entitled "Extensible Wormhole Routing Concentrator" by John Hesse and Coke Reed as inventors. [0007] 5. US Patent Application Serial No. 09 / 693603 entitled "Scalable Interconnect Architecture for Parallel Computing and Parallel Memory Access" by John Hesse and Coke Reed as inventors. [0008] 6. US Patent App...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56
CPCH04L49/3027H04L49/254H04L49/101H04L49/103H04L49/205H04L49/253
Inventor C·S·里德D·墨菲
Owner INTERACTIC HLDG LLC