Design verification using formal techniques

Abstract

Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and / or verification of sequential operations.

Description

technical field [0001] The present invention relates to design verification, and more specifically, to formal analysis verification techniques. Background technique [0002] Verification of a circuit design involves testing the circuit design before it is physically realized (eg, fabricated as an integrated circuit). In this way, design errors (ie, bugs) can be identified, allowing designers to avoid losses during production. [0003] As circuit designs become more complex, it becomes increasingly difficult to create an effective verification tool. For example, a traditional system-on-a-chip includes a relatively large, fast, and complex integrated memory, an on-chip bus, and a complex arbiter. Also, these designs often include parallel processes that may depend on each other. [0004] Traditionally, simulation-based tools have been used to verify designs. These tools typically verify the entire design by randomly applying tests to portions of the design. However, simul...

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Problems solved by technology

[0007] However, most formal techniques cannot be effectively used for relatively large industrial designs

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