Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

Abstract

A synchronous mirror delay (600) includes a model delay line (610) that is coupled to a bi-directional delay line (602). In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The (SMD) thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Description

technical field [0001] The present invention relates generally to integrated circuits, and more particularly to synchronizing an internal clock signal generated in the integrated circuit with an external clock signal applied to the integrated circuit. Background technique [0002] In a synchronous integrated circuit, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memory (SDRAM), synchronous static random access memory (SSRAM), and memory cartridges such as SLDRAM and RDRAM, as well as other types of integrated circuits , for example, a microprocessor. The timing of external signals that synchronize memory devices is determined by an external clock signal, and it is often necessary to synchronize operations within the memory d...

AI Technical Summary

Problems solved by technology

Additionally, it is difficult to achieve the required delay resolution in SMD 300 due to inherent problems associated with properly sizing the NMOS and PMOS transistors in unit delays 310A-N, as will be appreciated by those skilled in the art

As the frequency of operation increases, even small changes in the variable delay VD can cause undesirable delays or jitter in the CLKSYNC signal relative to the CLK signal

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