Nucleus logic chip for computer system

Abstract

The invention relate to a core logic chip, applied to a computer system with a CPU and a peripheral device, and comprising a programmable interrupt controller, connected to the peripheral device and able to respond to an external interrupt signal that the peripheral device sends out so as to send out a control signal by an interrupt signal pin, as the operating system of the computer system has not been loaded yet; an I / O first-in programmable interrupt controller, connected with the peripheral device and able to respond to the external interrupt signal so as to send out an interrupt control packet with interrupt vector to the CPU, as the operating system has been loaded and the programmable interrupt controller is disabled; and a virtual wiring connection functional block, connected to the interrupt signal pin of the programmable interrupt controller to respond to the control signal so as to send out a virtual connection interrupt packet to the CPU.

Description

technical field [0001] The invention relates to a core logic chip, in particular to a core logic chip applied to a computer system. Background technique [0002] See figure 1 , which is a schematic diagram of the interrupt control architecture of the central processing unit in a commonly used computer system. After the peripheral device 11 sends an external interrupt signal to the South Bridge chip (South Bridge) 12, the external interrupt signal will be sent to the programmable South Bridge chip 12. An interrupt controller (Programmable Interrupt Controller, referred to as PIC) 121, after the programmable interrupt controller 121 receives the external interrupt signal, it will notify the central processing unit (CPU) 13 that there is an external interrupt signal through the interrupt signal pin (INTR) Produce, after central processing unit 13 receives notification, just read the interrupt vector (interrupt vector) data about this external interrupt signal to programmable i...

AI Technical Summary

Problems solved by technology

[0007] However, some operating systems (such as Novell's Netware version 5.1 and version 6.0) find that the system has an I / O Advanced Programmable Interrupt Controller (I / O APIC) during the loading process, and they will automatically execute it. Initialization action, and the whole content of redirection table (redirection table) will be cleared wherein, cause the 8th bit to the 10th bit of entry0 can not keep as 111 all the time, make to solve the interrupt signal connection of central processing unit 33 with virtual line mode The problem mechanism that the pin (INTR) is omitted is destroyed, so when an interrupt signal is generated at this moment, the central processing unit 33 will not be notified, which will cause a problem in the interrupt control and produce a system crash state

[0008] And how to solve the above-mentioned interrupt control problem caused by the improper initialization of the input and output advanced programmable interrupt controller (I / O APIC) by firmware or software, so that the computer system has a higher reliability of interrupt control, for Main purpose of developing the present invention

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