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Digital lock detector in use for phase locked loop

A technology of detectors and phase-locked loops, applied in the field of phase-locked loops, can solve problems such as variation effects and unstable performance

Active Publication Date: 2010-05-05
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the lock detector is formed with an analog circuit, there will be some components of resistance or capacitance, which are easily affected by the variation of the manufacturing process, temperature, and power supply, making its performance unstable. Therefore, the lock detector is constructed digitally. It has become one of the common means to overcome the aforementioned shortcomings

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  • Digital lock detector in use for phase locked loop
  • Digital lock detector in use for phase locked loop
  • Digital lock detector in use for phase locked loop

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Embodiment Construction

[0026] figure 2 It is a structural diagram of a phase-locked loop using a lock-in detector, which includes a phase-frequency detector (phase frequency detector; PFD) 21, a low-pass filter 23, and a voltage-controlled oscillator (voltage controlled oscillator; VCO ) 25 and a lock detector 30. A reference clock Ref passes through the loop formed by the phase frequency detector 21, the low-pass filter 23 and the voltage-controlled oscillator 25 (i.e. the basic phase-locked loop) to generate a feedback clock output Fed; the lock detector 30 is used to detect the lock Whether the phase loop enters a locked state, and outputs a locked signal to indicate that the feedback clock output Fed enters a locked state.

[0027] Please refer to Figure 3A , which is a schematic structural diagram of a phase-locked loop using a lock-in detector according to an embodiment of the present invention. The PLL 10 generates a feedback clock Fed according to a reference clock Ref. The lock detecto...

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Abstract

The lock detector is suitable for a phase locked loop. Based on a reference clock, the phase locked loop generates a feedback clock. The lock detector includes a match detector and an arbitrator. Whenfirst clock is carrying a switch at a switching point, the match detector is in use for checking whether a switching point of second clock is fallen into a preset time window. The preset time windowcontains the switching point of the first clock. When the switching point of the second clock is fallen to the preset time window, the match detector outputs a match signal. The arbitrator is in use for calculating continuous occurring number of the said match signal, and examining whether the said continuous occurring number is accorded with first preset standard; if yes, the arbitrator outputs alock signal to present that the feedback clock enters into a lock state.

Description

technical field [0001] The present invention relates to a phase locked loop (PLL), and more particularly to a digital lock detector for a phase locked loop. Background technique [0002] In current synchronous systems (such as computer systems and communication equipment), the clock generation circuit is a very important part. With the rapid increase of the operating speed of the circuit, the performance requirements of the clock generation circuit are also more stringent. It is very important for the system to determine when the clock is stable and available for logic operations. This function is often called lock detection and is usually performed by a lock detector. If the lock detector is formed with an analog circuit, there will be some components of resistance or capacitance, which are easily affected by the variation of the manufacturing process, temperature, and power supply, making its performance unstable. Therefore, the lock detector is constructed digitally. It...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H04L7/00
Inventor 陈永聪徐亚涛宋振宇李耿民
Owner VIA TECH INC