Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrode; a first wiring layer that is provided on the first insulating resin layer and is connected to the electrode through the first opening; a second insulating resin layer provided over the first insulating resin layer and the first wiring layer, the second insulating resin layer having a second opening that is defined at a position different from the position of the first opening in a direction of the surface of the semiconductor substrate; and a second wiring layer that is provided on the second insulating resin layer and is connected to the first wiring layer through the second opening, wherein the second wiring layer includes an induction element, and a sum of a thickness of the first insulating resin layer and a thickness of the second insulating resin layer is not less than 5 mum and not more than 60 mum.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, wherein the formation of a semiconductor having an inductive element formed on a semiconductor substrate such as a silicon wafer is accomplished together with its packaging. [0002] Priority is claimed on Japanese Patent Application No. 2004-221785 filed on July 29, 2004 and Japanese Patent Application No. 2004-302696 filed on October 18, 2004, the contents of which are incorporated herein by reference. Background technique [0003] In recent years, in the manufacture of high-frequency semiconductor elements, in order to ensure impedance matching and the like, inductive elements, such as spiral inductors, are formed on semiconductor substrates. In such a semiconductor element, however, due to parasitic capacitance between the wiring and the semiconductor substrate, part of the electromagnetic energy generated by the inductive element is lost in the substrat...

AI Technical Summary

Problems solved by technology

[0023] (1) Because the lower wiring layer 21 is close to the semiconductor substrate 1, C Si energy loss due to increased parasitic capacitance

[0024] (2) Since the lower wiring layer 21 and the upper wiring layer 23 (helical coil 24) are close, C S increase, resulting in energy loss

[0026] (1) Because the lower wiring layer 24 is close to the semiconductor substrate 1, R Si Increased due to eddy current losses resulting in energy loss

[0027] (2) Since the lower wiring layer 21 and the upper wiring layer 23 (helical coil 24) are close, C S increase, resulting in energy loss

[0029] However, in conventional semiconductor devices, multilayer wiring structures may be required

In this case, impedance mismatch occurs at junctions (contact holes) connecting wires and inductive elements formed in different layers, which can lead to a decrease in quality factor value (Q value)

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