38results about How to "Avoid Impedance Mismatches" patented technology

The embodiment of the invention provides an ultra-low noise tile-type phased array plane based on a silicon-based chip, and the phased array plane comprises an antenna part PCB, and the antenna part PCB comprises an array antenna, an LNA chip, a board-level filter, a BFIC chip based on a silicon-based technology, and a power division network which are connected in sequence; wherein the array antenna is provided with a patch antenna, and a feed point of the patch antenna is directly connected with the LNA chip through a plated-through hole; the LNA chip is connected with the board-level filter through a plated-through hole, the board-level filter is connected with the BFIC chip through a plated-through hole, and the BFIC chip is connected with the power division network through a plated-through hole; the LNA chip is integrated with a dynamic tuning matching circuit, and dynamic impedance matching can be carried out according to the working condition of the patch antenna. Therefore, the tile-type phased array plane provided by the embodiment of the invention realizes the consideration of high integration level, low noise, low loss, dynamic matching and interference resistance, and overcomes the defects of the traditional tile-type phased array plane in the aspects of integration level, noise, loss, matching flexibility, filtering and the like.