Sample-and-hold circuit and driver circuit
A technology for driving circuits and holding circuits, which can be applied to instruments, static indicators, etc., and can solve problems such as buffer 6 and amplifier circuit errors
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no. 1 example
[0036] Refer to attached figure 1 , which depicts a first embodiment of the present invention. figure 1 is a circuit diagram showing the sample and hold circuit 100 of this embodiment. Such as figure 1As shown, the sample and hold circuit 100 includes a first analog switch 101 (SW_RH), a second analog switch 102 (SW_RL) and a differential amplifier 103 . The impedance of the analog switch 101 is greater than the impedance of the analog switch 102 . The analog switches 101 and 102 are connected in parallel to a first input terminal of a differential amplifier 103 . It should be noted that, figure 1 A capacitance 104 is shown in , which can be assumed to be a parasitic capacitance.
[0037] Refer to attached figure 2 and 3 , describing the working process of the sample and hold circuit 100. figure 2 and image 3 is a timing chart and an output waveform diagram illustrating the sampling operation of the sample and hold circuit 100. figure 2 In the case shown, eit...
no. 2 example
[0043] refer to Figure 4A and 4B , to describe the second embodiment of the present invention. Figure 4A denotes a capacitor array type analog / digital converter 200, Figure 4B A switching element 201 used in this analog / digital converter 200 is shown. The second embodiment describes a capacitor array type analog / digital converter 200 using switching elements 201, such as Figure 4B As shown, the higher impedance analog switch 101 (SW_RH) and the lower impedance analog switch 102 (SW_RL) in the switching element 201 are connected in parallel. The analog / digital converter 200 converts input data into an analog voltage.
[0044] Such as Figure 4A As shown, the analog / digital converter 200 includes a capacitor array 202 and an output buffer 203 having an operational amplifier or the like and connected to an output line of the capacitor array 202 . The capacitor array 202 includes 2n capacitors, whose capacitances are respectively set to c, c / 2 according to the number of ...
no. 3 example
[0050] refer to Figure 5 , to describe the third embodiment of the present invention. Figure 5 It is a drive circuit 300 provided with a precharge circuit. Such as Figure 5 As shown, the driving circuit 300 includes: a voltage divider circuit 301 , a decoder 302 and an output buffer 303 . In this illustrative embodiment, capacitor 304 is inserted between decoder 302 and output buffer 303 . This capacitor can be a parasitic capacitance. In addition, the decoder 302 is provided with a precharge circuit (not shown) for charging the capacitor 304 provided between the decoder 302 and the output buffer 303 .
[0051] According to the externally applied input signal voltages Q0, Q1 (Q0<Q1), the voltage divider circuit 301 generates 2n grayscale voltages. In this illustrative embodiment, these two input signal voltages are applied externally. However, the present invention is not limited thereto, and two or more voltages may be applied externally. The grayscale voltage gener...
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