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Method and device for asynchronously computing timing coutrol instruction for multi-address space

A timing control and multi-address technology, applied in the direction of machine execution devices, etc., can solve complicated and other problems, and achieve the effect of simple structure, avoiding long-term non-stop, and flexible application

Inactive Publication Date: 2006-05-24
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, timer setting requires multiple instructions, which is more complicated in applications that frequently use timers

Method used

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  • Method and device for asynchronously computing timing coutrol instruction for multi-address space
  • Method and device for asynchronously computing timing coutrol instruction for multi-address space
  • Method and device for asynchronously computing timing coutrol instruction for multi-address space

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Embodiment Construction

[0022] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] With reference to Fig. 1, timing control device of the present invention comprises instruction decoder 1, timing control unit 2, general-purpose register group 3, timing register 4 and timer 5, and the output end of instruction decoder 1 is respectively with timing control unit 2, The input end of general-purpose register group 3 and timing register 4 is connected, and the output end of general-purpose register group 3 is connected with the second input end of timing register 4, and the output end of timing register 4 is connected with the input end of timer 5, and timer 5 The overflow signal output terminal of the overflow signal is connected with the other input terminal of the timing control unit 2, and the two control signal output terminals of the timing control unit 2 are respectively connected with the third input terminal of the timing register 4 and th...

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Abstract

The method includes steps: (1) obtaining the source and pattern codes by decoding instruction; (2) determining initial value of timer based on the source; (3) carrying out operations of starting, stopping and resetting timer based on pattern codes; (4) timing overflow of timer generates abnormal signal to report error. Embedding timing control unit to architecture of general processor without adding additional module, the method realizes instruction of timing control. Using one piece of instruction of timing control instead of timing operation implemented by multiple instructions usually, the invention solves issues of no response for error of asynchronous calculation as well as not ending for long time caused by error of transferring blocks with multiple addressing spaces. Features are simple structure and flexible application.

Description

technical field [0001] The invention relates to a method and a device for asynchronously computing timing control instructions in multiple address spaces. Background technique [0002] Computation-intensive applications often use a host-accelerator structure to improve computing efficiency. There is a large-scale data transmission between the host and the accelerator, and it is easy to cause the transmission process to continue for a long time due to errors in the transmission path. In addition, if there is an asynchronous calculation unit in the accelerator, the asynchronous calculation of the unit may also fail to output calculation results and response signals for a long time due to errors. For the detection of such common error problems, it is usually realized by timer programming. However, timer setting requires multiple instructions, which is complicated in applications that frequently use timers. Contents of the invention [0003] The object of the present inventi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
Inventor 沈海斌季爱明
Owner ZHEJIANG UNIV
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