54 results about "Asynchronous computation" patented technology

In embodiments of the present invention improved capabilities are described for a computer program product embodied in a computer readable medium that, when executing on one or more computers, receives a request for game play, and in response to the request, causing prior game play data to be retrieved, where the prior game play data was stored in response to prior game play of another user. Further, an asynchronous game play environment may be provided where an active participant, who made the request, is able to play against and interact with an apparently live participant based on the prior game play data.

A method and a system implementing asynchronous computation batching. A web application written in a side-effect free manner possesses the quality of referential transparency. This property allows independent functions to be executed in any order or in parallel and enables necessary data for such functions to be gathered in a batch query. This property also extends to dependent functions and allows web applications to be written assuming random access to data on a database.

An embodiment of the invention discloses an optimized web paging query method and device. The optimized web paging query method includes asynchronously calculating a page range and a total record number: after a paging query request for an appointed page is received, firstly calculating the page range and then acquiring data loading display within the page range; and after a request for calculating the total record number is received, detecting whether a matched total record number is saved in a cache or not, if not, calculating the total record number and updating the same in the cache, and if so, reading the total record number from the cache directly. Through asynchronous calculation, the responding speed of web paging query is increased; by means of saving the total record number via the cache, the number of times for accessing to a database during web paging query is decreased, and loading efficiency is improved.

The invention provides a synchronous detection method for TD-LTE (time division long term evolution) network optimized equipment. The synchronizing with a base station is finished by fully using the hardware (mainly comprising an FPGA (field programmable gate array) and a CPU (central processing unit)) of the existing network optimized equipment. The method comprises the steps that a near end generates a synchronous switch signal according to an input signal and transmits the switch signal to each far end; each far end controls a radio frequency switch to realize uplink-downlink switching according to the switch signal. As the CPU is not a special signal processing chip, the CPU cannot realize real-time treatment under the condition of larger delay (time for calculating SSS once is at second level) and an LTE (long term evolution) semi-frame being 5ms long when massive data are processed. The method adopts an asynchronous calculation mode, so the demand on real-time property is reduced. The demand on the real-time property of the CPU is not high, a GPS (global positioning system) module and a modem do not need to be connected, the equipment cost is reduced, and the structure is more compact.

Some of the most advanced fireworks displays incorporate music, video, lights, and other special effects. For the seamless operation of these displays, the presence of computerized firing systems on the market can be greatly appreciated. In addition to entertainment value, the abilities of initiating a fireworks display from a distance and being able to stop a display at any time has made shooting fireworks displays safer than ever. However, because of the expense of this hardware, these elaborate displays can be far out of reach for anyone who has a lower budget. The idea outlined in this patent will help solve that issue by suggesting an asynchronous computerized firing system. This system can be initiated using a personal computer without any proprietary hardware with the exception of low cost modules.

The invention belongs to the category of high-speed large-capacity data measurement and recording. By adopting methods of synchronous parallel sampling, sectionally synchronous transmission, data queue synchronization, sectionally synchronous computing, parallel synchronous recording, on-line synchronous timing and accurate marking of absolute time of sampling data, and the like, the sectional computing synchronization and the accurate synchronization recording of a plurality of sub-recorders under an asynchronous computation process in a distributed-type integrated recorder are realized. A system clock provides the guarantee for synchronous parallel sampling and sectionally synchronous transmission. Parallel buses and control circuits which are integrated on the sub-recorders and a motherboard are taken as a synchronous hardware basis. The data queue synchronization and the computing and recording synchronization can be realized by matching a queue synchronization control line and a status line, a calculation synchronization control line and a status line as well as a recording, recorded value and definite value control line and a status line with a motherboard synchronization control circuit. The method conveniently and reliably ensures the strict synchronization of data recording of the distributed-type integrated recorder and the high-resolution time precise positioning of data mutation or scheduled events.

The invention provides a structural-dynamic-analysis explicit-different-step-length parallel computing method. The method includes the four steps that (1) data files required by parallel computing aregenerated with the partition multiple-node strategy; (2) time step lengths of all partitions are selected according to partition unit characteristics to be subjected to explicit prediction step computing; (3) in small-step-length partitions, partition-inside and boundary-node data is solved through step-by-step decreasing of the explicit sub-cycle process, and in large-step-length partitions, inside and boundary-node data is solved through the main time step length; (4) the boundary-node data required by paralleling is received by all the partitions, partition information is updated, strainsand stress are computed as required, and partition node data is output; if a main time step is ended, the program is stopped, and if a main time step is not ended, the step (2) is newly carried out. According to the structural-dynamic-analysis explicit-different-step-length parallel computing method, in the large-scale dynamic parallel analysis process, different time step lengths can be selectedaccording to the partition unit characteristics, partition different-step computing coupling is achieved with the multiple-node strategy, and parallel efficiency is effectively improved.

The invention provides a method for cooperatively computing and accelerating pre-stack time migration of an earthquake by using a CPU (Central Processing Unit)/MIC (Microphone), and relates to the field of high-property computing. According to the method, a CPU and MIC heterogeneous framework is used; a CPU is in charge of performing FFT (Fast Fourier Transform) computing, reading seismic channel data, performing process control and scheduling, and further participating in PSTM (Photon Scanning Tunneling Microscope) computing; the MIC is used for only performing the PSTM computing, and simultaneously performing CPU and MIC cooperative computation and common computation in an asynchronous parallel idea and dynamic load balance manner; and the integrated design comprises the following three aspects: parallel design of a PSTM computation partial serial algorithm, a PSTM integrated logic structural design and a CPU and MIC asynchronous computation design. The method provided by the invention has the beneficial effects that the PSTM properties can be improved by using the CPU/MIC cooperative computation; the building cost and management, operation and maintenance costs of a machine room can be reduced; and the simple realization and the low desired development cost can be realized.

The invention belongs to the technical field of power systems and automation thereof, and discloses a forced oscillation disturbance source positioning method based on frequency band-dividing parallel computation. A preset frequency range is divided into a plurality of frequency bands for parallel computation; as for each frequency band, through setting each data window length and each sampling frequency, analyzed data points are reduced; each frequency band adopts an asynchronous computation mode, other frequency bands do not need to be waited after one-round analysis computation, a result is refreshed and new data are obtained for next-round analysis, dissipation power of a unit, a transformer and a line is calculated, a suspected oscillation source related element is screened according to a threshold value, oscillation elements are grouped according to a dominant mode phase angle, and elements with advanced phases in the group of the suspected oscillation source elements are selected as the oscillation source unit, the related line and the transformer. The scheme is reasonably designed, and forced power oscillation warning and disturbance source positioning information timeliness can be ensured.

The invention discloses a data verification acceleration method and device, computer equipment and a storage medium. The method comprises the steps of obtaining to-be-verified data; performing segmentation processing on the to-be-verified data based on the standard data size of the preset data block, and determining a plurality of verification blocks, the verification data size of the verification blocks being equal to the standard data size of the preset data block; obtaining a request message sent by an upper computer, and judging whether the request message is a verification request or not; if the request message is a verification request, executing an asynchronous verification processing program to verify the multiple verification blocks, wherein the asynchronous verification processing program comprises an interrupt processing program and an asynchronous calculation program, the interrupt processing program is used for sending a verification waiting response to the upper computer, and the asynchronous calculation program is used for calculating the verification blocks; and sending a verification response to the upper computer after the calculation is finished. According to the invention, the processing speed of data verification is improved by expanding the data size of the verification block for each verification processing and adopting an asynchronous calculation method to perform data verification.

The invention discloses an asynchronous high energy efficiency map computing accelerator, which includes sequentially connected data preprocessing module, data transmission module and data processingmodule, wherein: the data preprocessing module preprocesses a given example graph G in an initialization stage, partitions large-scale graph data, and further organizes the graph G into a sub-graph data Batch Row Vector with batch_size as a size; the data transfer module transfers the sub-graph data Batch Row Vector to the on-board DDR via PCIe DMA, and then to the on-chip accelerator via AXI DMA.The data processing module is an accelerator on-chip logic, comprising a memory module and a calculation module. The memory module comprises an on-chip cache, and the computing module comprises an on-chip computing module. The invention designs the asynchronous high energy efficiency map computational accelerator, adopts the asynchronous calculation mode to accelerate the convergence speed of themap algorithm, and customizes the accelerator based on the hardware platform to reduce the power consumption and the energy consumption of the system.

The embodiment of the invention provides an asynchronous calculation method and device for a network function in a spreadsheet. The method comprises the following steps that: a first thread obtains the function information of a network function to be calculated; the first thread searches a calculation result corresponding to the function information in a first cache region; if the calculation result corresponding to the function information is not found in the first cache region, the first thread stores the function information to a second cache region; and the second thread obtains the function information from the second cache region; according to the function information, network function calculation is carried out, the calculation result is stored to the first cache region, and the first thread is started to search the calculation result corresponding to the function information. By use of the method, the asynchronous calculation of the network function is realized, time for a userto wait for the network function to return the calculation result can be shortened, and user experience is improved.

A method includes retrieving a first dataset at a first frequency from a memory, the first dataset associated with a plurality of data objects; calculating at the first frequency and based on the first dataset, a first component for each of the data objects; retrieving a second dataset at a second frequency from the memory, the second dataset associated with the plurality of data objects; calculating at the second frequency and based on the second dataset, a second component for each of the data objects; weighting at one of the first or second frequencies, the first component by the second component for each of the data objects; calculating at one of the first or second frequencies, an asynchronous multi-component index based on the weighted first component; and generating at least one asynchronous multi-component index data object having a value that is determined from the calculated asynchronous multi-component index.

The invention relates to a data processing method, device, system and equipment and a storage medium, is applied to a calculation processing server, and comprises the following steps: receiving a data calculation request which is sent by the data processing server and carries a data processing result of an editing cell; in response to the data calculation request, updating data in a target cell associated with the editing cell in the target table based on the data processing result to obtain a data updating result of the target cell; and sending the data updating result to the client. According to the method and the device, asynchronous calculation is carried out by the independent calculation processing server, so that calculation service with higher expandability is independent.

The method includes steps: (1) obtaining the source and pattern codes by decoding instruction; (2) determining initial value of timer based on the source; (3) carrying out operations of starting, stopping and resetting timer based on pattern codes; (4) timing overflow of timer generates abnormal signal to report error. Embedding timing control unit to architecture of general processor without adding additional module, the method realizes instruction of timing control. Using one piece of instruction of timing control instead of timing operation implemented by multiple instructions usually, the invention solves issues of no response for error of asynchronous calculation as well as not ending for long time caused by error of transferring blocks with multiple addressing spaces. Features are simple structure and flexible application.

The invention discloses a method for dynamically calculating an MD5 value in a storage device, which is applied to the storage device in which an object storage S3 protocol and a file storage NAS protocol are intercommunicated to realize dynamic calculation of the MD5 value. When an object is uploaded through an NAS protocol, an MD5 value is calculated online in real time; when the object is modified in a modified writing or additional writing mode, the MD5 value is modified to be in a temporary state, meanwhile, a calculation task is created to asynchronously calculate the MD5 value, and the priority of the calculation task is set; and the background thread periodically enumerates the calculation task for calculation. Counts are set in a frequent object modification scene, and when the object is modified, the counts are increased if a previously created calculation task is not executed, so that repeated calculation is avoided; in order to reduce CPU consumption caused by frequent modification, a validity period is set, if an object is modified in the validity period, only the MD5 value is modified to be in a temporary state without calculation, and if a user needs to check the MD5 value in the validity period, an asynchronous calculation task is created, and the priority of the calculation task is improved.