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General in-situ programmeable gate array configuration wiring model

A layout and routing, gate array technology, applied in the field of VLSI, can solve problems such as complex structure of FPGA

Inactive Publication Date: 2006-05-24
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Academia and industry have conducted extensive research on logic blocks and wiring structures. However, most of these research works are based on academic research, and industrial FPGA structures are relatively more complex.

Method used

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  • General in-situ programmeable gate array configuration wiring model
  • General in-situ programmeable gate array configuration wiring model
  • General in-situ programmeable gate array configuration wiring model

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0051] In order to illustrate the method used herein, the technical solutions and implementation steps herein are described in detail for specific examples.

[0052] (I) Improvement of the connection box CB

[0053] In this model, the flexibility of CB is extended to specify the connection between any pin and the routing resources in the channel, so that the VPR model is no longer limited to the singleness of the pin connection.

[0054] Take the alu4 test circuit in Table 1 as an example, the specific method is as follows:

[0055] For the pins of the model of the present invention, there are the following connections:

[0056] β(P 1 )=(1, TOP, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0) the first pin, the position is on the top, and the pin is connected with the third, seventh, and tenth horizontal wiring resources no connection

[0057] β(P 2 )=(2, BOTTOM, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1) the second pin, the position is below, and the pin is the second, fourth, sixth, eighth Routing r...

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Abstract

The invention belongs to technical area of very large-scale integrated circuit, specific to layout and wiring model of general field programmable gate array. Based on VPR scientific model, the disclosed model improves connection box (CB) model and switching box model (SB) in VPR. Thus, the possessing representative ness, comparative flexibility, the new model can process structure of CB and SB in FPGA. Based on the model, combining relevant method of software process, the invention starts from an initial FPGA structure, changes structure of CB and SB, and finds optimal structure of CB and SB relevant to this FPGA structure. Test result shows that the disclosed model possesses important guiding effect for optimizing FPGA structure.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuits, and in particular relates to a layout and wiring model irrelevant to the specific structure of FPGA. Background technique [0002] Since Xilinx launched FPGA (Field Programmable Gate Array) in 1985, FPGA has been widely used. Initially, FPGAs were used for small-batch production such as prototypes, and could only implement simple digital circuits; as FPGAs improve in terms of speed, power consumption, and integration, today's FPGAs can implement complex digital systems including memory and processors. , the integration level of the chip reaches 10 million gates, and the speed reaches 300MHz. In addition to the manufacturing process, most of this huge change is the result of structural improvements. Academia and industry have conducted extensive research on logic blocks and wiring structures. However, most of these research works are based on academic research, and ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 唐璞山陈苑锋来金梅童家榕
Owner FUDAN UNIV
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