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Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter

A technology with modular structure and low power consumption, which is applied in the direction of analog-to-digital converters, etc., and can solve the problems of multiple current sources, excessive parasitic gate-to-drain capacitance, and high power consumption

Inactive Publication Date: 2006-05-24
FUDAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a hybrid two-layer folded circuit for high-speed low-power folded structure analog-to-digital converters, so as to overcome the shortcomings of the existing folded circuit with many current sources, high power consumption, and excessive parasitic gate-to-drain capacitance.

Method used

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  • Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter
  • Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter
  • Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter

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Embodiment Construction

[0017] Further describe the present invention below in conjunction with accompanying drawing.

[0018] The connection diagram of the commonly used folding circuit 20 is as follows figure 2 shown. The figure is the most important part, such as the circuit configuration form of the current source is not given in the figure. However, this does not affect the use of this figure to help understand the generation of folding signals. The components used in the circuit 20 include n-channel MOSFET (NMOS) transistors 60-77, current sources 81-89 and resistors 221-222. There are mainly two circuits, one is the amplifier circuit 21 and the other is the output circuit 22 . The amplifying circuit 21 is composed of M identical basic differential amplifying units, where M=9 is taken as an example, namely: basic differential amplifying units 211 - 219 . Take unit 211 as an example to illustrate its circuit connection. Unit 211 is composed of a pair of input differential transistors 60-61 ...

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Abstract

The disclosed circuit is composed of amplifying circuit and output circuit. The amplifying circuit includes M pieces of identical amplifying unit in two layers. These amplifying units carry out amplification for 3í‡M pairs of difference input voltage. These difference inputs are supplied by outputs from preamplification, sample and hold unit. Output circuit consists of two pieces of resistance. Comparing with number of power supply in traditional folding circuit, the number of power supply needed in the invention is reduced greatly. Moreover, since number of transistor in difference input connected to output node is reduced greatly, parasitic capacitance between grid and drain poles at output node is reduced greatly.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a hybrid two-layer folded circuit for high-speed and low-power folded structure analog-to-digital converters. Background technique [0002] As a bottleneck in mixed-signal SoCs, high-speed analog-to-digital converters consume significant die area, power consumption, and design time. At the same time, high-speed medium-resolution analog-to-digital converters are widely used in high-speed data communications, liquid crystal display drivers, digital oscilloscopes, and hard disk drive circuits. Among many kinds of analog-to-digital converter circuit structures, the folded structure has the advantages of high speed, small area and easy compatibility with digital technology. [0003] Compared with the all-parallel analog-to-digital converter, the folding analog-to-digital converter greatly reduces the number of comparators due to the use of folding circuits, an...

Claims

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Application Information

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IPC IPC(8): H03M1/12
Inventor 任俊彦毛静文姚炳昆林俪许俊
Owner FUDAN UNIV
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