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Integrated memory device and memory module

A storage device and storage module technology, applied in information storage, static memory, memory systems, etc., can solve problems such as bit rate increase

Inactive Publication Date: 2006-09-13
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such a high bit rate cannot be handled technically, neither by the data port of the storage device, nor by the bus channel and the memory controller, so according to the above-mentioned DDR-4 approach, either an increase in the number of pins is accepted, or Accept bitrate increase

Method used

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  • Integrated memory device and memory module
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  • Integrated memory device and memory module

Examples

Experimental program
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Embodiment Construction

[0021] figure 1 A storage device 1 including a memory array 2 is shown. The memory array includes memory cells 3 arranged on word lines 4 and bit lines 5 . The storage unit may be, for example, a DRAM storage unit, an SRAM unit, or the like.

[0022] The memory device 1 is designed, for example, as a double data rate memory device from which data can be read in burst access, which means that by applying an address to the memory array 2, some data bits are provided internally , and thus output in groups of parallel data bits in consecutive cycles.

[0023] This can be achieved, for example, by simultaneously addressing multiple memory areas (memory banks, etc.), which provide data to be read out from the addressed memory cells 3 and appending the read data to the prefetch buffer 6 , where data is latched until it is appended to the output through some output port 8. Prefetch is performed by the prefetch readout unit 9 .

[0024] In traditional storage devices, the number o...

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Abstract

The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2of the sets of addressable memory cells.

Description

technical field [0001] The present invention relates to an integrated memory device comprising a plurality of memory cells which are addressable by addresses, wherein data is denoted by 2 n groups of bits to prefetch. The invention further relates to a memory module comprising a plurality of memory means. Background technique [0002] In a DDR (Double Data Rate) memory device, data in a memory cell can usually be stored in 2 n Groups of bits or multiples thereof are addressed by addresses. When data is retrieved from the memory location, each group of bits addressed by the address is prefetched in the prefetch buffer. Once the data from the addressed memory area is stored in the prefetch buffer, the data is usually output through the output port in a sequence of continuous cycles, a so-called data burst. Data is output with the rising and falling edges of the clock signal according to the double data rate technique, and the number of output cycles depends on the number o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/00G11C7/10H01L27/10
CPCG06F12/0862G06F2212/6022
Inventor C·西歇尔特H·鲁克鲍尔D·萨维纳克P·格雷戈里乌斯P·瓦尔纳
Owner INFINEON TECH AG