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Bus hold circuit with power-down and over-voltage tolerance

A technology for holding circuits and buses, which is applied in the field of CMOS bus holding circuits and bus holding circuits, and can solve problems including consumption of DC power.

Inactive Publication Date: 2006-09-13
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But in order to sense the occurrence of overvoltage, said circuit unfortunately contains many components and consumes DC power

Method used

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  • Bus hold circuit with power-down and over-voltage tolerance
  • Bus hold circuit with power-down and over-voltage tolerance
  • Bus hold circuit with power-down and over-voltage tolerance

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Embodiment Construction

[0023] figure 2 The method of the present invention is shown in block diagram form. In this circuit, a separate power connection, called prail, is provided to the power supply portion of the bus holding circuit, providing the higher of Vin and Vcc as determined by the prail arbitration circuit 20 discussed below. In this block diagram, P3 connects Vcc to the latched inverter formed by N2 and P2. When Vin exceeds Vcc, P3 turns off, preventing leakage current from flowing from Vin to Vcc, as described for Figure 1A. Note that the prail only supplies power to the N-well of the PMOS transistor, it eliminates the leakage path from Vin to Vcc when Vin is higher than Vcc.

[0024] right figure 2 , testing three conditions:

[0025] First, the "normal" condition when Vin is at logic low. In this situation, Vcc appears on the prail through the arbitration circuit 20; P4 is turned on, driving the gate of P3 low to make it turn on. Vcc supplies power to the feedback inverter includ...

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PUM

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Abstract

A bus hold circuit of CMOS components that draws no DC current and is over voltage tolerant is described. No leakage current is drawn from the input when the input voltage is greater than the bus hold circuit supply voltage. A feedback inverter is used to s latch the Vin logic in the bus hold circuit. When Vin is low, it turns on a first switch that drives the gate of a PMOS switch low turning it on. The PMOS switch connects the power connection of the feedback inverter to Vcc. The gate remains low, keeping the PMOS switch turned on as Vin increases. The first switch is turned off, but the gate of the PMOS switch remains low, until Vin exceeds Vcc. At that point, a comparator drives the gate of the PMOS to Vin shutting the PMOS switch off. An arbiter circuit selects the higher of Vcc and Vin to bias the N-well of the PMOS switch and other PMOS components in the comparator and arbiter circuit. This biasing ensures that the N-wells are never forward biased, thereby preventing leakage from the Vin.

Description

technical field [0001] The present invention relates to a bus driver circuit, more specifically, to a bus hold circuit that maintains an output logic state when an input signal source exhibits a high impedance state; more specifically, to a CMOS bus hold circuit that is tolerant of overvoltage, power-off It creates no leakage paths and saves DC power and components. Background technique [0002] A conventional bus-hold circuit latches data from an input circuit while presenting a high-impedance load on the input circuit. Older bus-hold circuits tolerate neither loss of power nor overvoltage, in which case a fault or unacceptable condition would occur. For example, when a +5 volt logic system is connected to a +3.3 volt system, or is cut off instantaneously, an overvoltage phenomenon will occur: input signal overshoot occurs. A power outage occurs when part of the system loses power, such as for maintenance or to preserve battery life. When this happens, leakage currents c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/037H03K3/356
CPCH03K3/35613H03K3/356165H03K2217/0018H03K3/00H03K3/356G06F13/00G06F1/32
Inventor 迈伦·J.·米斯克斯蒂芬·B.·罗姆巴德
Owner FAIRCHILD SEMICON CORP