Memory subsystem and its method for generating latch clock

Abstract

Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Description

technical field [0001] The present invention relates to a memory subsystem, and more particularly to a method and system for generating a latch clock for reading memory. Background technique [0002] In many random access memory (RAM) architectures, two common forms of volatile RAM are dynamic random access memory (DRAM) and static random access memory (static random access memory). , SRAM). Each storage unit (or bit) of the SRAM is composed of a flip-flop, and a basic storage device usually requires about six transistors. In contrast, each bit of DRAM requires only one transistor, so DRAM is usually cheaper and more compact than SRAM. SRAM is generally faster than DRAM and easier to operate. Thus, SRAM is typically used in faster but smaller memory computing devices, while DRAM is typically used in computing devices requiring large amounts of random access memory. In fact, many microprocessor-based systems use a combination of DRAM and SRAM. DRAM chips are used to form ...

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However, it is still possible for this algorithm to select the operating point closest to the edge of the Shmoo graph

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