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Pseudo-random sequence generating device

A pseudo-random sequence and generating device technology, which is applied in the direction of pulse generation with a predetermined statistical distribution of parameters, etc., can solve the problems of slow data generation speed, etc., and achieve the effect of improving the generation speed.

Inactive Publication Date: 2006-11-08
HUAWEI TECH CO LTD
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Problems solved by technology

[0019] The biggest disadvantage of the existing technology is: the data generation speed is slow, and only 1 bit of data can be generated in one reference clock cycle. If you need to output kbit parallel data, you need to wait for k reference clock cycles. When the demand is for each reference clock When the kbit pseudo-random code is periodically output, the existing method cannot solve the problem

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Embodiment 1

[0065] Embodiment 1: A pseudo-random sequence generator that simultaneously generates a 5-bit PN3 sequence value at a time.

[0066] See Figure 4 , Figure 4 It is a schematic diagram of a pseudo-random sequence generating apparatus for generating 5-bit PN3 sequence values ​​at one time in Embodiment 1 of the present invention. Figure 4 The device shown includes five PN3 sequence generators with a phase interval of 5, namely the first PN3 sequence generator 401 with a phase interval of 5 to the fifth PN3 sequence generator 405 with a phase interval of 5, and a phase-shifting combinational logic processing unit. 406. The first PN3 sequence generator 401 with phase interval 5 to the fifth PN3 sequence generator 405 with phase interval 5 work in parallel, all access the reference clock with a period of T, and output one bit in each reference clock period. PN3 sequence value. A PN3 sequence generator with a phase interval of 5 completes the shift of 5 phases at a time, and i...

Embodiment 2

[0085] Embodiment 2: An optimization scheme of a pseudo-random sequence generator that simultaneously generates a 5-bit PN3 sequence value at a time.

[0086] See Figure 8 , Figure 8 It is a pseudo-random sequence generating device that simultaneously generates a 5-bit PN3 sequence value in the second embodiment of the present invention. Figure 8 The apparatus shown includes a PN3 sequence generator 801 with a phase interval of 5, two data transmission lines, and a combinational logic processing unit 804, wherein the combinational logic processing unit 804 includes a combinational logic circuit 802 that produces an output value of 4 and a combinational logic circuit 802 that produces an output value of 5. Combinatorial logic circuit 803. The PN3 sequencer 801 with phase interval 5 uses such as Figure 5 The shown PN3 sequence generator with a phase interval of 5, the device receives the seed number, and outputs the current value of SR0 in the included three shift registe...

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Abstract

This invention discloses two kinds of false random sequence generating devices, in which, the first one includes: k false random sequence generators connected with a same reference clock to receive seed data and output 1 bit data in a period of the reference clock and output k bit data altogether as the data of the false random sequence to be output to outside and k is a natural number greater than 1, the second device contains one false random sequence generator, the phase interval of which is t, a natural number larger than 1, which can output multiple bit false random codes in each reference clock period to increase the generation velocity of data flows.

Description

technical field [0001] The present invention relates to the generation technology of pseudo-random sequence, in particular to a pseudo-random sequence generating device. Background technique [0002] Pseudo-random sequence, also known as pseudo-random code or pseudo-random noise (PN, Pseudo Noise) code, has certain definite coding rules and is easy to repeatedly generate and process, so it is widely used in the field of communication. There are many ways to generate pseudo-random sequences. Usually, the circuit for generating pseudo-random sequences is a feedback shift register. It can be divided into linear feedback shift register and nonlinear feedback shift register two categories. The pseudo-random sequence generator mentioned below refers to the linear feedback shift register. [0003] Usually, the pseudo-random sequence generator includes multiple shift registers (SR, shift registers) and some combinational logic circuits, and generates binary sequence values ​​throu...

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Application Information

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IPC IPC(8): H03K3/84
Inventor 王小璐
Owner HUAWEI TECH CO LTD
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