33 results about "Nonlinear feedback shift register" patented technology

The invention relates to an encoding solution to three quasic-low-density parity-check (QC-LDPC) codes with different code rates in a digital television terrestrial multimedia broadcasting (DTMB) system. The encoding solution is characterized in that an encoder for the QC-LDPC codes in the system mainly comprises six parts, including a task scheduling module, a barrel shift accumulation circuit, a linear feedback shift register circuit, a convolution sum circuit, a modified shift register and accumulation circuit and an rearrangement splicing circuit.

An embodiment of the invention provides a non-linear feedback shift register. A data distributing network selects variables from state values according to a logical operation function and outputs the variables; a calculating network performs logical conjunction operation and exclusive disjunction operation on the variables inputted by the data distributing network; non-linear feedback functions of a cryptographic algorithm can be converted into functions which only comprises logical conjunction and exclusive disjunction, the logical operation function for the data distributing network of the non-linear feedback shift register in an embodiment consists of logical conjunction operation and exclusive disjunction operation, and calculation carried out by the calculating network also consists of logical conjunction operation and exclusive disjunction operation, so that data can be selected and calculated according to different non-linear feedback functions. The non-linear feedback shift register is widely suitable for different cryptographic algorithms.

The invention discloses a database data encryption system and a method thereof. The system comprises a model Q nonlinear feedback shift register, a permutation table replacement module, a substitution transforming module and an operation module; wherein, the model Q nonlinear feedback shift register is used for nonlinear feedback by taking the specified key as initial value, the feedback value is replaced and converted by the preset substitution list to continuously generate derived keys with 18 states, and the generated derived keys are applied in encryption and decryption operation of all block ciphers; the permutation table replacement module is used for transforming by taking byte as unit; the substitution transforming module is used for replacing by taking byte as unit; the operation module is used for expanding or centralizing the data in a database according to the byte for lateral accumulating; under the indication of the derived keys which are replaced and transformed by the model Q nonlinear feedback shift register, replacement and substitution operation can be carried out, so that encryption and decryption of the data in the database can be completed. The invention can effectively protect the safety of the data in the database.

An all-optical linear feedback circuit for use, for example, as a maximal length pseudo random bit sequence generator includes an all-optical logic circuit that is capable of generating 2^N−1 bit maximal length pseudo random bit sequences on an optical channel at high data rates e.g. 80 Gbit/s. In the pseudo random bit sequence generator of the present invention, intensity-dependent phase modulation of at least one included semiconductor optical amplifier (SOA) is implemented. The maximum data rate is limited by the fast gain recovery time of the carriers in the SOA. An optical logic gate of the pseudo random bit sequence generator of the present invention may be constructed using various nonlinear elements that provide ultra-fast intensity-dependent phase modulation.

The invention relates to the field of integrated circuit testing and discloses a testing pattern generator of an integrated circuit, which consists of an I-typed linear feedback shift register, a decompressing circuit, a Johnson counter and an XOR gate network; wherein the I-typed linear feedback shift register has clock frequency of f1 and a generating sequence Q that is equal to (Q1Q2...Qm), and m is a natural number; the decompressing logic circuit has an output sequence S that is equal to (S1S2...SmSm+1...SN); the Johnson counter has a clock frequency of f2 and a generating sequence J that is equal to (J1J2...JmJm+1...JN), N is a natural number and N is more than m; the XOR gate network has an output sequence X that is equal to (X1X2...XmXm+1...XN) which is a output sequence of the testing pattern generator; and the clock frequency of the Johnson counter f2 is equal to 2 multiplied by N multiplied by f1; the I-typed linear feedback shift register, the decompressing circuit, the Johnson counter and the XOR gate network satisfy the following logic relation: (a) S equals to V multiplied by Q and (b) X equals to J XOR S.

An encryption and decryption method based on zipper type dynamic hashes and NLFSRs comprises the following steps that a nonlinear feedback function and a bit transformation Boolean function are used for preprocessing a seed secret key to form a secret key stream sequence; changing the bit value of the plaintext sequence according to the bit transformation Boolean function based on the key stream sequence to form a pseudo plaintext sequence; dividing the pseudo-plaintext sequence into a plurality of paths of pseudo-plaintext subsequences according to the key stream sequence; and calculating a dynamic hash address corresponding to the binary bit of each pseudo plaintext sequence according to a hash mapping rule depending on the key stream sequence, and mapping the pseudo plaintext subsequence hashes which are divided into multiple paths into a ciphertext space to form the ciphertext stream sequence. The method has the beneficial effects that the key stream generator not only uses a nonlinear feedback shift register, but also introduces a bit transformation Boolean function, so that the key stream with longer period and better randomness is obtained; and through a plaintext bit transformation rule and a zipper type dynamic hash mapping rule, the decoding difficulty of the ciphertext stream sequence is improved.

The invention relates to a sequence cipher realization device and a sequence cipher realization method thereof. The method comprises the following steps: firstly, generating a sequence source by adopting Galois-structure nonlinear feedback shift registers designed based on mixing and diffusion parts as a sequence source drive; and then, after the registers load keys, initialization vectors and constant parameters completely, carrying out idle operation for a certain number of beats, carrying out nonlinear operation on an output of the diffusion unit so that the output is taken as a key stream sequence, and carrying out exclusive or operation on the key stream sequence together with a plaintext sequence to form a ciphertext. According to the sequence cipher realization device and the sequence cipher realization method thereof disclosed by the invention, relatively less operation and hardware cost can be used; through combined use of the mixing unit and the diffusion unit, after multiple times of iterations, a pseudorandom sequence is output; according to hardware resource and speed requirements, the deployment and the implementation are flexible; and the requirements of communication for diverse networks and devices are met.

A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (mε|N) in a predetermined manner which is known on the decryption side, i.e. in that every m^th bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.

Shift registers are cipher components used for generating pseudo random sequences in the field of secret communication, comprising linear feedback shift registers LFSRs, non-linear feedback shift registers NLFSRs, and so on, wherein the maximum period T of the shift register is not greater than 2n. The feedback mode of an n-level non-linear cyclic shift register NRR refers to the following formula, in the formula, i>=0, n>=2, word length m is determined by the number of bits of a platform; <<<j represents ring shift left with j bits; a symbol referring to the description represents modular addition; c is an odd number within the range from 1 to 2<m>-1; initial values a<0>-a<n-1>of n inputted words are unlimited, and each word is an arbitrary m-digit number. When the word length is m bits, the period of the n-level non-linear cyclic shift register NRR is greater than (2<m>)<n>, i.e., the security of the n-level non-linear cyclic shift register NRR is better than the security of a traditional (non-)linear feedback shift register (N)LFSR, and the efficiency of the n-level non-linear cyclic shift register NRR is also better than the efficiency of a common (non-)linear feedback shift register (N)LFSR. The lightweight stream cipher LSNRR is designed through four non-linear cyclic shift registers NRRs, wherein the first NRR is used for secret key schedule, and modular addition is performed for outputs of the other three NRRs to generate a secret key stream of the LSNRR. The efficiency of the LSNRR is better than the efficiency of a common symmetric cipher, thus the LSNRR is suitable for the a resource-constrained environment and a resource-unconstrained environment, and is mainly used for data encryption and decryption.

Shift registers are cipher components used for generating pseudorandom sequences in the secret communication field and include linear feedback shift registers (LFSR), nonlinear feedback shift registers (NLFSR) and the like, and the maximum period T of the shift registers is smaller than or equal to 2n. The feedback mode of n stages of nonlinear ring shift registers (NRR) is shown in the specification, wherein i>=0, n>=2, the word length m is equal to the bit of a platform, <<<j represents ring shift left by j bits, the symbol in the specification represents modular addition, c is an odd number ranging from 1 to 2m-1, the initial values a0-an-1 of n input words are not limited, and each word has any m bits. When the word length is m bits, the period of the n stages of NRRs is larger than (2m)n, namely, the security is larger than that of traditional (N)LFSRs; the efficiency of the NRRs is also higher than that of common (N)LFSRs. The light-weight stream cipher LSNR2 is designed through 3 NRRs, wherein the first NRR is used for key scheduling, and output of the other two NRRs is subjected to modular addition to generate a key stream of the LSNR2. The efficiency of the LSNR2 is higher than that of common symmetric ciphers, and the LSNR2 is suitable for resource-constrained environments and is mainly used for encrypting and decrypting data in information systems.

An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

The invention discloses a hardware implementation device and method for a Fruit-80 ultra-lightweight encryption algorithm. The hardware implementation device comprises a key rotation function, a nonlinear feedback shift register, a linear feedback shift register, a key stream output function and a state control unit. The key rotation function is used for providing two key correlation bits; each of the nonlinear feedback shift register and the linear feedback shift register comprises a nonlinear feedback function and a linear feedback function; the key stream output function extracts the internal states of the nonlinear feedback shift register and the linear feedback shift register in each round, and generates a key stream for encryption; and the state control unit is used for coordinating the state updating of the nonlinear feedback shift register and the linear feedback shift register in the password stage of the device. According to the hardware implementation device and method disclosed by the invention, the hardware resource occupation of the Fruit-80 ultra-lightweight sequence cipher can be reduced, and the throughput rate of the Fruit-80 ultra-lightweight sequence cipher can be improved to the greatest extent.

The invention discloses a quantum random number post-processing device based on a nonlinear feedback shift register. The quantum random number post-processing device comprises an input unit, an arithmetic unit and an output unit, and the input unit comprises a plurality of bit input channels, and each channel inputs one bit of data into the arithmetic unit after passing through one clock. The quantum random number post-processing device has the beneficial effects that the classical randomness in the original data can be better removed by using the quantum random number processing algorithm ofthe non-linear feedback shift register, the quantum randomness is reserved, and the algorithm is better than an algorithm using a linear feedback shift register in the aspects of uniformity, unpredictability and the like of the final output data.

The invention provides a lightweight key sequence generator based on a chaotic system and an FPGA, and solves the problem that the precision of the chaotic system is limited by hardware resources. Thelightweight key sequence generator comprises a sequence generator module based on a Logistic chaotic system, two nonlinear shift registers, three data selection modules, a filter function H module and an output function Z module. According to the lightweight key sequence generator, a Logistic chaotic sequence is digitalized and is combined with a nonlinear feedback shift register through a certain algorithm; the chaotic system and the non-linear feedback shift register are well combined, and the FPGA-based hardware implementation ensures the pseudo-randomness of the sequence and the securityof the system, enables the code scale to be smaller, and occupies less hardware resources.

The invention provides a method and a system for generating n stages of pseudorandom sequences at least close to a maximum length using a non-linear feedback shift register (NLFSR), wherein the maximum length is 2n-1. The method comprises the following steps of: selecting n taps in the maximum-length linear feedback shift register, wherein n needs more than two taps; and for the selected n-level registers, generating a pseudorandom sequence by using a feedback logic operation of only the first logic gate and the second logic gate. The two suitable non-end taps are inputs for the first logic gate, the output of the first logic gate and the end tap are inputs for the second logic gate, and the output of the second logic gate serves as feedback to the first stage of the n-stage register.

The shift register used in system of providing enciphering code and deciphering code has one n-th order linear feedback shift register to provide polynomial coefficients and one memory to store calculation result with the polynomial coefficients of the linear feedback shift register and the received input sample. The memory has one input end to receive input sample and one output corresponding to the polynomial coefficients of the linear feedback shift register.

The invention provides encryption and decryption algorithms and a data encryption device. A data encryption method comprises the following steps: acquiring encryption parameters in a first linear feedback shift register and a second linear feedback shift register; encrypting encryption data in a feedback module according to the encryption parameters to obtain single-bit byte data; executing xor operation on the single-bit byte data and programming parameters to generate single-bit encrypted data. With adoption of the method, the security of one-way data transmission of half-duplex low-frequency RFID is improved, and the method has the advantages of being high in encryption and decryption speed, easy to implement, high in encryption strength, good in security and wide in application, and is applicable to software and hardware.