Test graph builder of integrated circuit

Abstract

The invention relates to the field of integrated circuit testing and discloses a testing pattern generator of an integrated circuit, which consists of an I-typed linear feedback shift register, a decompressing circuit, a Johnson counter and an XOR gate network; wherein the I-typed linear feedback shift register has clock frequency of f1 and a generating sequence Q that is equal to (Q1Q2...Qm), and m is a natural number; the decompressing logic circuit has an output sequence S that is equal to (S1S2...SmSm+1...SN); the Johnson counter has a clock frequency of f2 and a generating sequence J that is equal to (J1J2...JmJm+1...JN), N is a natural number and N is more than m; the XOR gate network has an output sequence X that is equal to (X1X2...XmXm+1...XN) which is a output sequence of the testing pattern generator; and the clock frequency of the Johnson counter f2 is equal to 2 multiplied by N multiplied by f1; the I-typed linear feedback shift register, the decompressing circuit, the Johnson counter and the XOR gate network satisfy the following logic relation: (a) S equals to V multiplied by Q and (b) X equals to J XOR S.

Description

technical field [0001] The invention relates to the field of testing of integrated circuits, in particular to a test pattern generator for integrated circuits. Background technique [0002] A traditional test pattern generator (Test Pattern Generator, TPG for short) is generally implemented by a linear feedback shift register (Linear Feedback Shift Register, LFSR for short). With the acceleration of integrated circuit test frequency, the test power consumption is getting bigger and bigger. In order to reduce the test power consumption, a series of solutions have been proposed: one is to reduce the test clock frequency, but this will prolong the test cycle and reduce the test efficiency; the other is to use the enhanced flip-flop to isolate the target logic of the circuit under test and the scan chain, thereby reducing power consumption, but this will cause the performance of the circuit under test to degrade, and generate relatively large hardware overhead; one is to use ti...

AI Technical Summary

Problems solved by technology

In order to reduce the test power consumption, a series of solutions have been proposed: one is to reduce the test clock frequency, but this will prolong the test cycle and reduce the test efficiency; the other is to use the enhanced flip-flop to isolate the target logic of the circuit under test and the scan chain, thereby redu

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