Lightweight key sequence generator based on chaotic system and FPGA

Abstract

The invention provides a lightweight key sequence generator based on a chaotic system and an FPGA, and solves the problem that the precision of the chaotic system is limited by hardware resources. Thelightweight key sequence generator comprises a sequence generator module based on a Logistic chaotic system, two nonlinear shift registers, three data selection modules, a filter function H module and an output function Z module. According to the lightweight key sequence generator, a Logistic chaotic sequence is digitalized and is combined with a nonlinear feedback shift register through a certain algorithm; the chaotic system and the non-linear feedback shift register are well combined, and the FPGA-based hardware implementation ensures the pseudo-randomness of the sequence and the securityof the system, enables the code scale to be smaller, and occupies less hardware resources.

Description

technical field [0001] The invention belongs to the field of information security hardware system encryption, in particular to a light-weight key sequence generator based on a chaotic system and FPGA. Background technique [0002] In the prior art, the lightweight sequence cipher based on FPGA basically adopts traditional nonlinear feedback shift register (NFSR) and linear feedback shift register (LFSR) to realize; combined, [0003] Chaotic systems have many advantages such as initial value sensitivity, unpredictability, fractal properties, and universality. The digitized chaotic sequence also continues the advantages of the chaotic system to a certain extent, so it is especially suitable for encryption systems. With the development of society, lightweight serial ciphers emerge as the times require, which are suitable for applications in resource-constrained devices. [0004] In order to avoid the precision limitation of the digital chaotic system implemented by hardware...

AI Technical Summary

Problems solved by technology

[0004] In order to avoid the precision limitation of the digital chaotic system implemented by hardware, resulting in poor pseudo-randomness of the chaotic sequence and low security of the chaotic system, when designing the chaotic system, it will be expressed with a larger bit width as much as possible, but this requires a lot of Hardware resources, that is, the accuracy of the chaotic system is limited by hardware resources

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