Method for fabricating chalcogenide-applied memory
A chalcogenide and elemental compound technology is applied in the field of reducing the contact area of a chalcogenide memory cell and forming its insulating area, and can solve the problems of reducing the current and energy required for switching
Inactive Publication Date: 2007-02-28
MACRONIX INT CO LTD
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- Application Information
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Problems solved by technology
However, in some chalcogenide memories, the area of the "filament" can be reduced to be smaller than the cross-sectional area of the memory cell, which further reduces the current and energy required for switching
Method used
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[0039] Before describing in detail one or more embodiments of the invention, those skilled in the art should understand that the invention is not limited to the detailed description of construction in the specification, the arrangement of components and the arrangement of steps illustrated in the following detailed description or drawings. The invention is capable of other embodiments and of being carried out or being carried out in various ways. It is also to be understood that the grammar and phraseology used herein are for the purpose of description only and should not be regarded as limiting.
[0040] 1 is a cross-sectional view of a first embodiment of a chalcogenide memory cell 100 according to a first embodiment of the present invention, wherein tapered holes are formed in the bottom electrode by anisotropic etching, and the chalcogenide Material and top electrodes 110 are deposited in the holes to reduce the effective electrical contact area of the memory cell 100 . ...
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A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.
Description
technical field [0001] Embodiments of the present invention relate to a method of fabricating a chalcogenide memory, and more particularly to a method of reducing a contact area of a chalcogenide memory cell and forming an insulating area thereof. Background technique [0002] Multimedia applications in communication components, computers, and consumer electronics have increased the demand for memory components, and these applications have also increased the need for compliance with memory components. Increasing memory device requirements include, but are not limited to, high density, non-volatility, high-speed access, low power consumption, and good endurance. Developments in current memory devices to meet these needs include, but are not limited to, flash, magnetic, magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and chalcogenide memory. Chalcogenide memory includes, but is not limited to, Ovonic Unified Memory such as ECD Ovoni...
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IPC IPC(8): H01L45/00H01L27/24G11C11/56H10N80/00
CPCH01L27/2409H01L45/141H01L45/1666H01L45/1273H01L45/1683H01L45/04H01L45/1233Y10S438/90H10B63/20H10N70/20H10N70/826H10N70/8418H10N70/882H10N70/061H10N70/066
Inventor 薛铭祥
Owner MACRONIX INT CO LTD