Current-controlled cmos delay cell with variable bandwidth

Abstract

Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Description

technical field [0001] The present invention relates to the field of communication equipment, and more specifically, relates to a delayed cell implemented in the communication equipment. Background technique [0002] Data communication systems have undergone continuous development over the years. In many broadband data communication system applications, variable delay cells are used. In these applications, however, it is often required to adjust the timing control between the different components. One such application of delay cells is in a delay locked loop (DLL). A common way to design a DLL is to use many delay blocks. In the previous technology, each independent delay block will bring high energy consumption. Designing a more energy-efficient delay block is worth looking forward to. [0003] Proper positioning and control of the different elements within a communication system often require safeguards by which the various signals are conditioned to ensure proper pos...

AI Technical Summary

Problems solved by technology

In the previous technology process, each independent delay block will bring higher energy consumption

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