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Method of manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as steep concentration distribution, difficulty in reducing parasitic resistance, and inability to highly activate impurities

Inactive Publication Date: 2007-04-11
FUJITSU SEMICON LTD
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Therefore, if annealing is performed by heating at a high temperature, a steep concentration distribution cannot be obtained, and besides, the resistance Rov increases
On the other hand, if the annealing treatment is performed at a low temperature at which a steep concentration profile of impurities can be obtained, the impurities cannot be highly activated and the resistances Rext, Rdp, and Rco increase
Therefore, it is difficult to reduce all the resistances Rext, Rdp, Rco, and Rov, so that it is difficult to reduce the parasitic resistance in the source / drain to a sufficient degree
In this way, it is difficult to achieve high performance when the gate length of the miniature CMOS transistor is not longer than 30nm

Method used

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Examples

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no. 1 example

[0063] A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1-16B. First, the principle of the manufacturing method of the semiconductor device according to the present embodiment will be described below. The first feature of this embodiment is that the first annealing treatment is performed by using the rapid thermal annealing system, and after the first annealing treatment, the annealing time is performed by using the LSA (laser flash annealing) system or the FLA (flash lamp annealing) system. The second annealing treatment not longer than 100 milliseconds. The second feature of this embodiment is that a substance for controlling diffusion is introduced into the source / drain diffusion layer for controlling the diffusion of impurities in the extension region. That is, the present embodiment has the feature of combining the first feature and the second feature described above....

no. 2 example

[0095] A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described below with reference to FIGS. 17-24. First, the principle of the manufacturing method of the semiconductor device according to the present embodiment will be described below. 17 is a graph showing the concentration distribution of impurities (boron), where the abscissa represents the depth (nm) from the substrate surface, and the ordinate represents the impurity concentration in logarithmic form (cm -3 ). Curve e1 represents the concentration profile immediately after boron implantation, and curve e2 represents the concentration profile after annealing treatment by the rapid thermal annealing method. Curve e3 shows the concentration profile after millisecond annealing at an annealing temperature of 1350°C, and curve e4 shows the concentration profile after millisecond annealing at an annealing temperature of 1350°C followed by rapid thermal annea...

no. 3 example

[0110] Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 25 and 26 . FIG. 25 is a flowchart showing a method of manufacturing a semiconductor device according to this embodiment. The flowchart shown in FIG. 25 is characterized in that after forming the deep source / drain regions at step S30 and before performing rapid thermal annealing at step S31 as shown in the flowchart of FIG. 18 of the second embodiment, A step 30' of millisecond annealing is added. That is, as shown in FIG. 18, the second embodiment includes the step of performing millisecond annealing after the step of forming the extension region (step S27) and after the step of rapid thermal annealing (step S31). In addition, this embodiment includes the step of performing millisecond annealing after the step of forming deep source / drain regions (step S30 ) and before the step of rapid thermal annealing (step S31 )....

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Abstract

It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S 1 ), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S 7 ), introducing a diffusion-controlling substance into the semiconductor substrate to control the diffusion of the impurity (step S 8 ), forming a side wall-insulating film on each side surface of the gate electrode (step S 9 ), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S 10 ), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S 11 ), and further activating the impurity by the millisecond annealing treatment (step S 12 ).

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device including a MOS (Metal Oxide Semiconductor) transistor having a source / drain extension structure. Background technique [0002] In recent years, it has been hoped to develop a laser annealing technology as a next-generation heat treatment process to replace rapid thermal annealing. This technology is a non-equilibrium heat treatment process, which is a melting recrystallization process in an extremely short time of a few nanoseconds, which provides the advantages of high electrical activity when the solid solution of impurities in the semiconductor is excessively limited, and Solid solutions of impurities in semiconductors are generally limited by temperature and steep impurity distribution; and source / drain electrodes with low contact resistance and shallower and steeper impurity diffusion (extension) regions can be formed. [0003] In order to improve the performance o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/324
CPCH01L21/823842H01L21/823814H01L21/26506H01L21/26513H01L29/7836
Inventor 山本知成久保智裕
Owner FUJITSU SEMICON LTD