Method of manufacturing symmetric arrays

Abstract

A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application No. 60 / 714,852, filed September 8, 2005, the entire contents of which are hereby incorporated by reference. technical field [0003] This application relates to symmetric memory arrays, and more particularly to contact areas therein. Background technique [0004] Symmetrical memory arrays are well known in the art. Reference is now made to one type of symmetric memory array shown in FIG. 1, which is typically used in NROM (Nitride Read Only Memory) arrays. It has columns of bit lines 10 and rows of word lines 12 intersecting the bit lines 10 extending across the array. The word lines 12 are grouped into regions 14 , wherein each region 14 is separated from each other by a contact region 16 . [0005] Contacts 18 in contact region 16 deliver power to bit line 10 , typically through contact ...

AI Technical Summary

Problems solved by technology

Contacts 18 are generally large and therefore cannot fit within the standard spacing of wordlines 12

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