Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A master control device with double CPU and realization method

A technology for master control equipment and mailboxes, which is used in instruments, electrical digital data processing, digital transmission systems, etc., and can solve problems such as small capacity and limited throughput.

Inactive Publication Date: 2007-05-16
NEW H3C TECH CO LTD
View PDF0 Cites 13 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The problem to be solved by the present invention is to provide a master control device with dual CPUs and an implementation method to solve the defects of small capacity and limited throughput caused by the single communication mode of the master-slave CPU in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A master control device with double CPU and realization method
  • A master control device with double CPU and realization method
  • A master control device with double CPU and realization method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] A first embodiment of a single-channel master control device with dual CPUs of the present invention, as shown in FIG. 3 , includes a master CPU, a slave CPU, a mailbox device, and a high-speed channel management device. Among them, the master CPU and the slave CPU are interconnected through the high-speed channel provided by the mailbox device and the high-speed channel management device. The mailbox device provides interrupt-level fast communication for emergency information between the master and slave CPUs. High-throughput information exchange, such as: transmitting analysis messages, query information and status information, etc.

[0046] Among them, the mailbox device includes: dual-port RAM, or ordinary memory plus logic control device, or ordinary memory plus I / O controller and other devices capable of generating interrupt signals. The implementation process of interrupt-level fast communication specifically includes: when the slave CPU has emergency information...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The disclosed one-way primary control device with dual CPU comprises: a primary CPU connected the secondary CPU by e-mail and high-speed channel, an e-mail device to provide interrupt-level fast communication, and a high-speed channel to transfer information between dual CPU. This invention realizes large-capacity communication and fast process for emergent affairs.

Description

technical field [0001] The invention relates to communication equipment management technology, in particular to a main control equipment with dual CPUs (Central Processing Unit, central processing unit) and an implementation method. Background technique [0002] In the prior art, the circuit structure of one CPU is usually adopted, but the processing speed of one CPU is limited after all. In some application environments that require high processing speed, the processing speed can be increased by working together with two or more CPUs. In the existing dual-CPU system, a single channel interconnection is used between the master and slave CPUs, such as: shared memory, dual-port RAM (Random-Access Memory, random access memory), I / O (Input / Output, input / output) port, serial port, I2C (Inter-Integrated Circuit, internal integrated circuit bus) and other methods. [0003] An example of implementing a single channel interconnection in the way of shared memory is shown in Figure 1:...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04L12/24G06F15/167
Inventor 傅先刚李海燕焦旭坡
Owner NEW H3C TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com