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Method with high seam-filling ability and device structure obtained therefrom

A technology for filling trenches and dielectric layers, which is applied in the manufacture of electrical solid state devices, semiconductor devices, semiconductor/solid state devices, etc., can solve the problems of large ratio of trench depth to trench, device performance and electrical reliability, and process Limitations and other issues to achieve the effect of improving device reliability and performance

Inactive Publication Date: 2007-06-13
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, as devices require faster and faster designs, traditional processes and materials have process limitations
[0004] An example of such a process limitation deals with the difficulty of flushing trenches with high aspect ratios, which means that the ratio of trench depth to trench is large
High aspect ratios can cause problems in the trench fill process because the deposited material is not evenly distributed over the surface area of ​​the trench, resulting in overhangs of the deposited material at the corners of the trench and voids in the center of the trench
This can cause device performance and electrical reliability issues

Method used

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  • Method with high seam-filling ability and device structure obtained therefrom
  • Method with high seam-filling ability and device structure obtained therefrom
  • Method with high seam-filling ability and device structure obtained therefrom

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Embodiment Construction

[0021] The present invention is directed to integrated circuits used in the production of semiconductor devices and their processing. Specifically, the present invention provides a CVD deposition method with high gap filling capability and the resulting device structure. Merely as an example, this method is applied to fabricate shallow trench isolation (STI) regions. But it should be recognized that the present invention has a wider range of applicability.

[0022] 1A and 1B are scanning electron microscope (SEM) images of a cross-section of a silicon substrate, which show voiding in a conventional trench filling process. The deposition process is used to fill the high aspect ratio trenches formed in the substrate. For example, a high aspect ratio trench is a trench in which the ratio of trench depth to trench width is greater than 5:1. When performing the deposition process, a trench having a trench opening of 12 μm and a depth of 5000 Ȧ may cause a lot of problems. A major probl...

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Abstract

The method includes steps: forming first layer in groove to fill it in groove partially; removing at least a part of the first layer from the groove; in condition of temperature at least 700 dig.C and airflow ratio at least 1.6, forming second layer. The said airflow ratio is a ratio of airflows between rate of first airflow and rate of second airflow. In the specific implementation example, the method includes steps: under the said temperature and the airflow ratio, contaminant is removed from the first layer through reaction with the contaminant.

Description

Technical field [0001] The present invention is directed to integrated circuits used in the manufacture of semiconductor devices and their processing. Specifically, the present invention provides a CVD deposition method with high gap filling capability and the resulting device structure. Merely as an example, this method has been applied to fabricate shallow trench isolation (STI) regions. However, the present invention can be considered to have a wider range of applicability. Background technique [0002] Integrated circuits or "ICs" have evolved from a few interconnected devices made on a single silicon chip to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to win advances in complexity and circuit density (that is, the number of devices that can be assembled on a given chip area), the smallest device feature size, also known as device "geometry", has become more and more important for each generation of ICs...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/31H01L27/04
CPCH01L21/76224H01L21/02274H01L21/02271H01L21/31612H01L21/02164H01L21/0228
Inventor 汪钉崇
Owner SEMICON MFG INT (SHANGHAI) CORP