Transistor epitaxial wafer and transistor

A technology for epitaxial wafers and transistors, which is applied to transistors, semiconductor devices, electrical components, etc., can solve the problems of poor surface flatness and high diffusion coefficient of the non-alloy layer 14, and achieve low power consumption, good resistance, and reduced resistance. Effect

Inactive Publication Date: 2007-06-20
SUMITOMO CHEM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this makes the flatness of the surface of the n-type InGaAs non-alloy layer 14 worse.
On the other hand, when Se / Te with good doping efficiency is used as the n-type dopant material, it is beneficial to improve the flatness of the n-type InGaAs non-alloy layer 14 and reduce the contact resistance, but compared with Si, the diffusion coefficient High, diffusion to the emitter layer 5 may occur during growth

Method used

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  • Transistor epitaxial wafer and transistor
  • Transistor epitaxial wafer and transistor
  • Transistor epitaxial wafer and transistor

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no. 1 Embodiment approach

[0101] FIG. 1 shows an epitaxial wafer for HBT according to a first embodiment of the present invention. The HBT epitaxial wafer 100 is obtained on the basis of the above results, and the In in the n-type InGaAs non-alloy layer 10 0→x Ga 1→1-x In the graded As layer 10a, Si is used as the dopant between In composition 0-0.35, and Se is doped for the remaining In composition between 0.35 and uniform In composition.

[0102] The structure of the epitaxial wafer 100 for HBT is that on the semi-insulating GaAs substrate 1, n-type GaAs layers (for example, thickness 500nm, carrier concentration 3×10 18 cm -3 ) composed of n-type sub-collector layer 2, composed of n-type GaAs layer (for example, thickness 700nm, carrier concentration 1×10 16 cm -3 ) composed of n-type collector layer 3, composed of p-type GaAs layer (for example, thickness 80nm, carrier concentration 4×10 19 cm -3 ) The p-type base layer 4 composed of n-type In x Ga 1-x P layer (X=0.48) (for example, thickne...

no. 2 Embodiment approach

[0115] FIG. 5 shows an HBT according to a second embodiment of the present invention. This HBT 200 is formed using the epitaxial wafer of the first embodiment shown in FIG. 1 .

[0116] The main body of HBT200 is composed of an epitaxial wafer. The structure of this epitaxial wafer is that on a semi-insulating GaAs substrate 1, an n-type sub-collector layer 2 composed of an n-type GaAs layer is sequentially stacked, and an n-type sub-collector layer 2 composed of an n-type GaAs layer is sequentially stacked. type collector layer 3, p-type base layer 4 composed of p-type GaAs layer, composed of n-type In x Ga 1-x An n-type emitter layer 5 composed of a P layer (X=0.48), an n-type emitter-collector layer 6 composed of an n-type GaAs layer, and an n-type InGaAs non-alloy layer 10 .

[0117] The n-type InGaAs non-alloy layer 10 consists of a first graded layer 7 doped with Si, a second graded layer 8 doped with Se, and an n-type In layer doped with Se. x Ga 1-x The homogeneous...

Embodiment approach

[0122] In addition, this invention is not limited to each said embodiment, Various deformation|transformation is possible in the range which does not deviate from or change the technical idea of ​​this invention.

[0123] For example, in the above-mentioned embodiment, the In composition of the uniform composition layer 9 is fixed at 0.5, but the In composition may be fixed at any value from 0.4 to 0.7.

[0124] In addition, the case where the n-type InGaAs heterogeneous composition layer (graded layer 10a) is a linearly graded layer in which the In composition gradually increases from 0 has been described, but it may also be a stepwise change in the In composition. gradient layer. Furthermore, instead of a gradient layer, the In composition of the first layer is in the range of 0 to 0.35, and the In composition of the second layer is inhomogeneous in the range of 0.35 to the In composition value of the uniform composition layer. layer.

[0125] in addition. In the above em...

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Abstract

The object of the present invention is to reduce the resistance for the n type InGaAs non-alloy layer. N type secondary collector layer (2), n type collector layer (3), p type base layer (4), n type emitter layer (5) and n type InGaAs non-alloy layer (10) are orderly formed on the semi-insulating GaAs substrate (1), the n type InGaAs non-alloy layer (10) is composed of a n type InGaAs gradual change layer (10a) having not homogeneous In composition (not homogeneous group layer) and a n type InGaAs homogeneous group layer (9) having homogeneous In composition. The n type InGaAs gradual change layer (10a) is composed of a first gradual change layer (7) (the first layer) with lower In composition and a second gradual layer (8) with higher In composition than that of the first layer. The first gradual layer (7) is adulterated with Si in order to restrain the background concentration of the C in the In composition and obtaining higher carrier concentration when adulterating Se as n type dopant.

Description

technical field [0001] The invention relates to an epitaxial wafer for a transistor and a transistor, in particular to the structure of its n-type InGaAs non-alloy layer. Background technique [0002] High-frequency devices using compound semiconductors represented by GaAs have small deformation and high-efficiency high-frequency characteristics above GHz, so they are widely used in amplifiers for mobile phones and other communication devices. Among them, a heterojunction bipolar transistor (hereinafter referred to as HBT) using a heterojunction in the emitter-base junction has a wider energy gap of the emitter layer than that of the base layer, so that the energy gap of the emitter can be improved. Because of its high injection efficiency, it has excellent high-frequency characteristics, and is widely used in high-output transistors for mobile phones, etc. [0003] In conventional HBTs, the emitter / base junction is generally formed by an AlGaAs / GaAs heterojunction, but in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/73H01L29/737
Inventor 守谷美彦
Owner SUMITOMO CHEM CO LTD
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