Method for creating a design verification test bench

a design verification and test bench technology, applied in the field of digital design verification, can solve the problem that the atpg techniques used in manufacturing test are not directly suitable for verification testing, and achieve the effect of large design

Inactive Publication Date: 2003-07-17
BUCKLEY DELMAS R JR
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Benefits of technology

0009] Waveforms are useful during the functional verification mode because they rapidly give a designer confidence that the circuit is working properly--it is important to remember that the goal here is to bring a very large design up to speed as rapidly as possible.

Problems solved by technology

The ATPG techniques used in manufacturing test are not directly suitable for verification testing and must be modified somewhat to provide useful test bench stimuli.

Method used

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  • Method for creating a design verification test bench
  • Method for creating a design verification test bench

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Embodiment Construction

[0014] FIG. 1 is a block diagram that illustrates a test bench creation system according to one aspect of the present invention. The system is designated generally by the reference numeral 100 and includes an HDL circuit design 102, a classified HDL circuit design 104, a test bench HDL design template 106, ATPG-like tools 108, designer interactions 110, 112, designer-selected parameters 114, and various ATPG-generated test stimuli and expected responses 116-122.

[0015] In general, a test bench creation process according to the present invention begins with a completed HDL circuit design 102. If the designer has not already done so, he now classifies 110 the various parts of the design according to circuit type, e.g., finite state machines (FSMs), data paths, counters, and shift registers. The classifications are typically entered directly into the HDL circuit design using special comment lines. The result of the designer intervention 110 is a classified HDL circuit design 104.

[0016] ...

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Abstract

A method for creating test benches for digital circuit design verification (1) partitions a design for purposes of test bench creation according to circuit type, (2) identifies circuit types and creates packaged testing strategies, (3) uses ATPG techniques to create comprehensive test sequences based on the circuit type classifications, and (4) incorporates the ATPG-produced test stimuli and expected responses into the test bench templates.

Description

RELATED APPLICATION[0001] This patent application is a continuation of U.S. patent application Ser. No. 09 / 740,632 filed Dec. 18, 2000, and claims benefit of the filing date thereof.FIELD OF THE INVENTION[0002] The invention relates to digital design verification, and more specifically to a method for creating a design verification test bench using automatic test pattern generation ("ATPG") and test strategies based on circuit-type classifications.BACKGROUND OF THE INVENTION[0003] Test benches for very large scale integrated circuit ("VLSI") designs are difficult and time consuming to create. Additionally, the complexity of circuits is not being fully explored during (non-formal) verification testing. The techniques now being used to create test benches rely on an application of human intuition in the form of waveform editing and test benches written in a hardware description language ("HDL"), such as Verilog and VHDL.[0004] These intuitive approaches suffer from the limitations tha...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F17/50
CPCG06F17/5022G06F30/33
Inventor BUCKLEY, DELMAS R. JR.
Owner BUCKLEY DELMAS R JR
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