Digital summing phase-lock loop circuit with sideband control and method therefor

Abstract

A digital summing phase-lock loop circuit with sideband control provides high accuracy and high speed acquisition in a multi-loop frequency synthesizer. A digital phase comparator is used to control a voltage-controlled oscillator in response to inputs from multiple external loops. An initial sweep condition is set by a sweep control circuit to provide resolution of lock ambiguities in the multiple external loops. Sideband selection may be performed by selecting on of an inverted or non-inverted output of the digital phase comparator.

Description

CROSS-REFERENCE TO RELATED PATENT[0001] The present application is related to U.S. Pat. No. 6,028,460 issued to the same inventors on Feb. 22, 2000. The specification of the above-referenced patent application is incorporated herein by reference.[0002] 1. Field of the Invention[0003] The present invention relates generally to frequency synthesizers, and more specifically, to a method and apparatus for reducing phase noise in synthesizers.[0004] 2. Background of the Invention[0005] Frequency synthesizers are primarily used in radio-frequency (RF) communications equipment, but have also found general-purpose application in digital computing systems as clock synthesizers and various other applications where precise signal generation and reception are critical.[0006] A phase-lock loop circuit typically is present at the core of a frequency synthesizer. A phase detector compares the output of the frequency synthesizer with a reference signal that may be divided down from a high-frequency...

AI Technical Summary

Problems solved by technology

Direct up-conversion or down-conversion of a high-frequency signal, while providing a simple single loop system, is typically not used in high accuracy synthesizer applications.

However, the phase comparison itself provides a theoretical and practical limit on synthesizer output phase noise because the phase noise of the phase comparator adds a contribution to the total phase noise at the synthesizer output.

Further, control of the sideband selection is complicated in a multi-loop synthesizer, as the loop can lock up at either the sum or difference frequencies of the combined signal.

Phase noise in a digital phase comparator is caused by any number of factors such as sampling hysteresis, non-linear or chaotic input circuit behavior and digital circuit jitter internal to the phase comparator.

However, the phase-lock loop disclosed therein is a single-loop system and the techniques disclosed do not apply directly to a multi-loop synthesizer, and does not provide a mechanism for preventing erroneous lock-up in a multi-loop configuration.

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