Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levels
a voltage level shifting and integrated circuit technology, applied in logic circuit coupling/interface arrangement, pulse technique, instruments, etc., can solve the problems of circuit implementations not only exhibiting operational speed problems, waste power, and low level translation speed, so as to increase the level translation speed of signals
Inactive Publication Date: 2004-07-29
PROMOS TECH INC
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- Description
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- Application Information
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Benefits of technology
"The patent text describes a circuit that can change the voltage levels of signals in an integrated circuit device. The circuit uses feedback to make the switching faster, which speeds up the process of translating signals between different power supplies. The circuit has multiple switching devices that are controlled by a control terminal, and a delay block is used to ensure the signals are properly synchronized. The technical effect of this circuit is to allow for faster and more efficient signal conversion in integrated circuit devices."
Problems solved by technology
With existing circuit techniques, the primary deficiency in operation is the speed at which the level translation occurs between signals based on the two different power supplies.
Certain conventional circuit implementations not only exhibit operational speed problems but can also waste power due to undesired current flow between a given power supply input and circuit ground.
Regardless of circuit design, existing level shifting schemes exhibit a negative impact on circuit speed performance.
Method used
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Embodiment Construction
[0013] With reference now to FIG. 1, a schematic diagram of a prior art voltage level shifting circuit 100 is shown. The circuit 100 comprises a P-channel transistor 102 in series with an N-channel transistor 102 coupled between a node N2 and circuit ground (VSS). The gates of the transistors 102 and 104 are connected to node N1 and the point intermediate the two devices defines a node N3.
[0014] In operation, if the node N1 voltage [V(N1)], when at a "high" logic level, is less than the voltage on node N2 [V(N2)], P-channel transistor 102 may not turn "off" when transistor 104 is turned "on". In this situation, current can flow from node N2 to circuit ground, thus wasting power.
[0015] With reference now to FIG. 2, a schematic diagram of another prior art voltage level shifting circuit 200 is shown. The circuit 200 comprises P-channel transistor 202 connected in series with N-channel transistor 204 between node N3 and circuit ground. Another P-channel transistor 206 in series with N-...
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A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speed of the level translation of signals based upon two different power supplies.
Description
BACKGROUND OF THE INVENTION[0001] The present invention relates, in general, to the field of integrated circuit ("IC") devices. More particularly, the present invention relates to a pre-biased voltage level shifting circuit of especial applicability with respect to those ICs requiring a technique for converting circuit operation between differing power supply levels.[0002] When different power supplies are required in a circuit, a means of transitioning between the differing supplies is required. With existing circuit techniques, the primary deficiency in operation is the speed at which the level translation occurs between signals based on the two different power supplies.[0003] Certain conventional circuit implementations not only exhibit operational speed problems but can also waste power due to undesired current flow between a given power supply input and circuit ground. In other circuits a "fight" condition can exist between transistors such that level shifting is slower in one ...
Claims
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IPC IPC(8): G11C7/10G11C11/4074H03K19/0185H03L5/00
CPCG11C7/1051H03K19/018521G11C11/4074G11C7/1057
Inventor MEADOWS, HAROLD BRETTFAUE, JON ALLAN
Owner PROMOS TECH INC