Semiconductor memory devices having offset transistors and methods of fabricating the same

Inactive Publication Date: 2005-02-10
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0016] The semiconductor memory devices according to some embodiments of the present invention may allow performing read

Problems solved by technology

However, DRAM memory devices require that a refresh operation be periodically performed in order to prevent data loss and thus DRAM memory devices consume power even when in a stand-by mode.
However, nonvolatile memory devices may require a higher voltage to perform a write operation.
However, if electric charges

Method used

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  • Semiconductor memory devices having offset transistors and methods of fabricating the same
  • Semiconductor memory devices having offset transistors and methods of fabricating the same
  • Semiconductor memory devices having offset transistors and methods of fabricating the same

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Embodiment Construction

[0024] The present invention will now be described more fully with reference to the accompanying drawings, in which typical embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer, element or substrate, or intervening layers and / or elements may also be present. In contrast, when a layer / element is referred to as being “directly on” another layer / element, there are no intervening layers or elements present. Likewise, when an element is described as being “between”...

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PUM

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Abstract

Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include word lines. One of these word lines may form the gate of the second planar transistor a unit memory cell.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2002-66086, filed Oct. 29, 2002, the contents of which are incorporated herein in its entirety by reference. FIELD OF THE INVENTION [0002] The present invention generally relates to semiconductor devices and more specifically, to semiconductor memory devices and associated methods of fabrication. BACKGROUND OF THE INVENTION [0003] DRAM semiconductor memory devices generally have a higher density of integration than do SRAM semiconductor memory devices. However, DRAM memory devices require that a refresh operation be periodically performed in order to prevent data loss and thus DRAM memory devices consume power even when in a stand-by mode. It is not necessary to perform a refresh process with nonvolatile memory devices such as a flash memory devices. However, nonvolatile memory devices may require a higher voltage to perform a write operation. [0004]...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/8247H01L29/72H01L27/115H01L29/423
CPCH01L21/28273H01L29/42324H01L27/11521H01L27/115H01L29/40114H10B69/00H10B41/30H01L29/72
Inventor AHN, SE-JINLEE, SE-HO
Owner SAMSUNG ELECTRONICS CO LTD
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