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Seed layer treatment

a seed layer and treatment technology, applied in the field of integrated circuit manufacturing, can solve the problems of affecting the deposition of the remaining material, the contamination of the thin and delicate seed layer, and the contamination of the organic material

Inactive Publication Date: 2005-05-26
DUBIN VALERY M +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, as the substrate is transferred, the thin and delicate seed layer is often contaminated.
Additionally, contamination with organic material may occur, for example from the person transferring the substrate.
Such contamination may result in defects which affect deposition of the material to form the remainder of the metal lines.
In fact, the metal lines formed over such defects are prone to include voids.
These voids may prevent transmissions through the metal lines, rendering the metal lines useless.
A die formed which includes such defects may fail testing and be discarded.
Unfortunately, surfactants of the cleaning solution are often incompatible with substances used during the deposition of the remainder of the metal line material.
As a result, the metal lines are still likely to include voids, rendering them useless.
In another attempt to remove contaminants from the seed layer prior to formation of metal lines, the substrate may be heated to temperatures in excess of about 300° C. Unfortunately, this may damage the thin and delicate seed layer.
Further, even upon exposure to such temperatures, certain contaminants as described above are likely to remain on the seed layer.

Method used

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Embodiment Construction

[0019] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0020] References to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) of the invention so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in one embodiment” does not necessarily refer to the same embodiment, although it may.

[0021] In various embodiments, a seed layer is treated to reduce contaminants before plating. In one embodiment a seed layer may be heated while in a reducing environment. In another embodiment, a seed la...

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Abstract

Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Description

[0001] This is a Divisional application of Ser. No.: 10 / 252,306 filed Sep. 23, 2002, which is presently pending.BACKGROUND [0002] 1. Technical Field [0003] An embodiment of the present invention relates to integrated circuit manufacturing, and in particular to a seed layer used to form an interconnect feature in an integrated circuit and / or package substrate. [0004] 2. Description of the Related Art [0005] In the fabrication of a die from a wafer, various materials may be deposited on a substrate of the wafer for various purposes. For example, a metal layer may be deposited on a patterned substrate to form interconnect features such as metal lines. The patterned substrate may include trenches within which the metal lines are formed. [0006] The substrate is generally of monocrystaline silicon material, such as silicon dioxide. The trenches may be defined within a silicon based inter-layer dielectric (ILD) material including an abundance of silicon, oxygen, and carbon elements. Additi...

Claims

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Application Information

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IPC IPC(8): B32B9/00C25D5/34H01L21/02H01L21/20H01L21/288H01L21/768
CPCC25D5/34H01L21/02068H01L21/2885Y10T428/24926H01L21/76861H01L21/76864H01L21/76873H01L21/76843
Inventor DUBIN, VALERY M.THOMAS, CHRISTOPHER D.CHIKARMANE, VINAY B.
Owner DUBIN VALERY M