Dual-scaler architecture for reducing video processing requirements

Abstract

A video signal processor includes an input port adapted to receive an input video signal. The input video signal is characterized by a first horizontal resolution and a first vertical resolution. The video signal processor also includes a prescaler adapted to perform prescaling of the video signal, wherein prescaling converts the input video signal at the first horizontal resolution and the first vertical resolution to a prescaled video signal characterized by a second horizontal resolution and a second vertical resolution. The video signal processor additionally includes a frame buffer coupled to the prescaler. The video signal processor further includes a horizontal scaler adapted to convert the horizontal scale of the prescaled video signal from the second horizontal resolution to a third horizontal resolution and a vertical scaler adapted to convert the vertical scale of the prescaled video signal from the second vertical resolution to a third vertical resolution.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS [0001] The present application claims benefit under 35 U.S.C. 119(e) of U.S. provisional application No. 60 / 558,647, filed Jul. 16, 2004, entitled “System And Method For Use In Video Processing Including A Programmable Input Device, A Pixel Clock Generator, And A Dual Scaler Architecture,” the contents of which is incorporated herein by reference in its entirety.STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] NOT APPLICABLE BACKGROUND OF THE INVENTION [0003] The present invention relates generally to integrated circuits (ICs), and more particularly to video processor ICs. More particularly, the present invention relates to an architecture for a video processor IC. Merely by way of example, the invention has been applied to a dual-scaler architecture adapted to reduce the workload of a video processor IC receiving high definition video signals. But it would be recognized that the method and ap...

AI Technical Summary

Benefits of technology

[0008] According to the present invention, techniques related to integrated circuits (ICs), and more particularly to video processor ICs, are provided. More particularly, the present invention relates to an architecture for a video processor IC. Merely by way of example, the invention has been applied to a dual-scaler architecture adapted to reduce the workload of a video processor IC receiving high definition video signals. But it would be recognized that the method and apparatus can be applied to both interlaced and progressive video signals and that the invention has a much broader range of applicability.

[0012] Numerous benefits are achieved using the present invention over conventional techniques. Some embodiments provide video processor ICs with reduced processor requirements. Additionally, embodiments of the present invention reduce the bandwidth of high definition signals for processing by deinterlacers adapted to process standard definition signals. Moreover, some embodiments of the present invention provide reductions in the manufacturing cost of video processor IC components as well as the cost of internal and external memories utilized in video processing operations. Furthermore, embodiments of the present invention provide methods and apparatus which reduce the power consumption for video processing ICs as well as video processing systems. Depending upon the embodiment, one or more of these benefits may exist. These and other benefits have been described throughout the present specification and more particularly below.

Problems solved by technology

For instance, as the clock rate of the video processing IC and the memory size provided increase, it becomes increasingly difficult to utilize hardware adapted for processing SDTV video signals to process HDTV video signals, while maintaining the resolution of the HDTV video signals.

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