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Memory

a technology of memory and polarization, applied in the field of memory, can solve the problems that the disturbance of these cells cannot be avoided, and achieve the effects of suppressing disturbance, suppressing polarization deterioration, and suppressing polarization deterioration

Inactive Publication Date: 2006-03-30
PATRENELLA CAPITAL LTD LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a memory that can suppress disturbance and improve performance. The memory includes a bit line and a word line, and a first storage means connected to the bit line and the word line. The memory applies a voltage pulse in opposite directions to at least non-selected first storage means to prevent polarization deterioration in the read operation. The memory can also apply a prescribed voltage to non-selected first storage means to equalize a variation of polarization quantity. By doing so, the memory can inhibit disturbance in the read operation and improve performance."

Problems solved by technology

In the aforementioned technique disclosed in Japanese Patent Laying-open No. 10-64255, however, no voltage is applied to those of the non-selected cells sharing the word and bit lines with the selected cell in the second procedure, and hence disturbance of these cells cannot be avoided.

Method used

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first embodiment

[0105] A simple matrix ferroelectric memory according to a first embodiment of the present invention is described with reference to read-rewrite and write operations collectively performed on all memory cells connected to an arbitrary word line WL.

[0106] The overall structure of the simple matrix ferroelectric memory according to the first embodiment is described with reference to FIG. 1. The ferroelectric memory according to the first embodiment comprises a memory cell array 1, a row decoder 2, a column decoder 3, a row address buffer 4, a column address buffer 5, a write amplifier 6, an input buffer 7, a read amplifier 8 consisting of a voltage sense amplifier, an output buffer 9 and a voltage generation circuit 10.

[0107] The memory cell array 1 includes a plurality of simple matrix memory cells consisting of only ferroelectric capacitors (not shown). The ferroelectric capacitors are examples of the “first storage means” in the present invention. The row and column decoders 2 an...

second embodiment

[0156] A simple matrix ferroelectric memory according to a second embodiment of the present invention is described with reference to a read amplifier 8a enabled to determine data while keeping a bit line BL substantially at 0 V in the overall structure of a cross-point ferroelectric memory similar to that according to the aforementioned first embodiment.

[0157]FIG. 37 illustrates the circuit structure of the read amplifier 8a according to the second embodiment. Referring to FIG. 37, a first resistor 16 has first and second ends connected to the bit line BL and an inverted input of an operational amplifier 18 respectively. The read amplifier 8a is an example of the “read data determination circuit” in the present invention. A non-inverted input of the operational amplifier 18 is grounded to 0 V. Therefore, the inverted input reaches 0 V in an initial state due to imaginary short of the operational amplifier 18. An output of the operational amplifier 18 is fed back to the inverted inp...

third embodiment

[0169] A simple matrix ferroelectric memory according to a third embodiment of the present invention is constituted to generate a reference voltage required for reading by reading data from dummy cells provided separately from memory cells for data storage.

[0170] The overall structure of the simple matrix ferroelectric memory according to the third embodiment is described with reference to FIG. 39. The simple matrix ferroelectric memory according to the third embodiment comprises a memory cell array 1a, a dummy cell array 1b, row decoders 2a and 2b, column decoders 3a and 3b, row address buffers 4a and 4b, column address buffers 5a and 5b, write amplifiers 6a and 6b, an input buffer 7, a read amplifier 8 consisting of a voltage sense amplifier, an output buffer 9 and a voltage generation circuit 10. The voltage generation circuit 10 is constituted to be capable of applying voltages ⅓Vcc and ⅔Vcc (see FIG. 2). Referring to FIG. 39, each dummy memory cell (dummy cell) located on the ...

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Abstract

A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

Description

[0001] This is a Divisional Application, which claims the benefit of pending U.S. patent application Ser. No. 10 / 792,926 filed, Mar. 5, 2004. The disclosure of the prior application is hereby incorporated in its entirety by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a memory, and more particularly, it relates to a memory having capacitance means and resistance means. [0004] 2. Description of the Background Art [0005] A method of reducing disturbance caused in a non-selected cell of a one-transistor ferroelectric memory is proposed in general. For example, Japanese Patent Laying-Open No. 10-64255 (1998) proposes such a method of reducing disturbance. In a data writing step disclosed in Japanese Patent Laying-Open No. 10-64255, voltages +V, ⅓ V, 0 V and ⅔ V are applied to a word line of a selected cell, the remaining word cells, a bit line of the selected cell and the remaining bit lines respectively as a first proced...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C5/14G11C7/12G11C11/22
CPCG11C7/02G11C11/22G11C7/12G11C7/18G11C8/14G11C11/225G11C11/2273G11C11/2275G11C11/2297
Inventor SAKAI, NAOFUMITAKANO, YOH
Owner PATRENELLA CAPITAL LTD LLC