Semiconductor damascene trench and methods thereof

Abstract

A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 09 / 943,078, filed Aug. 30, 2001 (MIO 0083 PA / 01-0459.00), now allowed. [0002] This application, which is also listed for clarity, is also a member of the following family of related U.S. patents: U.S. application Ser. No. 10 / 215,915 entitled CONDUCTIVE STRUCTURE FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING SUCH STRUCTURES, filed Aug. 8, 2002 (01-0334), now U.S. Pat. No. 6,879,507.BACKGROUND OF THE INVENTION [0003] The present invention relates in general to the fabrication of integrated circuits, and in particular to integrated circuit structures having damascene trench gates and local interconnects formed in a single process, and methods of fabricating such integrated circuit structures. [0004] Integrated circuit manufacturers continually strive to scale down semiconductor devices in integrated circuit chips. By scaling down semiconductor devices, greater ...

AI Technical Summary

Benefits of technology

This approach enables consistent and reliable formation of damascene gates and interconnects, reducing manufacturing costs and improving the performance of SRAM memory devices by minimizing the number of deposition and polishing processes.

Problems solved by technology

Further, as integrated circuits are scaled down, the complexity of fabricating the components that make up the devices continues to increase.

With the increase in complexity also comes an increase in the cost of fabricating the integrated circuits.

For example, as memory cells in SRAM continue to shrink, undesirable variations between desired results and actual results become a limiting factor because of the inherent limitations in many processes employed in the course of manufacturing.

For example, precision limits in photolithography, and deposition processes affect production parameters.

Also, every masking step that is performed during fabrication dramatically increases the cost of manufacturing a given device.

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