Semiconductor damascene trench and methods thereof
a damascene trench and damascene technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increasing the cost of fabricating integrated circuits, increasing the complexity of fabricating components that make up devices, and limiting factors such as undesirable variations between desired results and actual results, so as to reduce the length of gate lines and low resistance wordlines
Inactive Publication Date: 2006-12-14
MICRON TECH INC
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- Abstract
- Description
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- Application Information
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Benefits of technology
This approach enables low resistance wordlines, reduced gate length, and consistent formation of damascene gates and interconnects, thereby reducing manufacturing costs and improving the reliability of SRAM memory devices.
Problems solved by technology
Further, as integrated circuits are scaled down, the complexity of fabricating the components that make up the devices continues to increase.
With the increase in complexity also comes an increase in the cost of fabricating the integrated circuits.
For example, as memory cells in SRAM continue to shrink, undesirable variations between desired results and actual results become a limiting factor because of the inherent limitations in many processes employed in the course of manufacturing.
For example, precision limits in photolithography, and deposition processes affect production parameters.
Also, every masking step that is performed during fabrication dramatically increases the cost of manufacturing a given device.
Method used
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[0034] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration, and not by way of limitation, specific preferred embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention.
[0035] It shall be observed that the process steps and structures described herein do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with a variety of integrated circuit fabrication techniques, including those techniques currently used in the art. As such, commonly practiced process steps are included in the description herein only if those steps are necessary for an understanding of the present invention.
[0036] As used he...
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A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.
Description
CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present application is a division of U.S. patent application Ser. No. 10 / 883,522 (MIO 0083 VA / 01-0459.01) filed Jul. 1, 2004 which is a division of U.S. patent application Ser. No. 09 / 943,078 (MIO 0083 PA / 01-0459), filed Aug. 30, 2001, now U.S. Pat. No. 7,029,963 issued Apr. 18, 2006. This application is also related to U.S. patent application Ser. No. 10 / 215,915, filed Aug. 8, 2002, now U.S. Pat. No. 6,879,5078 and Ser. No. 11 / 348,149 (MIO 0083 NA / 01-0459.02), filed Feb. 6, 2006.BACKGROUND OF THE INVENTION [0002] The present invention relates in general to the fabrication of integrated circuits, and in particular to integrated circuit structures having damascene trench gates and local interconnects formed in a single process, and methods of fabricating such integrated circuit structures. [0003] Integrated circuit manufacturers continually strive to scale down semiconductor devices in integrated circuit chips. By scaling down semico...
Claims
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IPC IPC(8): H01L21/4763H01L23/48H01L21/762H01L21/768H01L21/8234H10B10/00
CPCH01L21/76224H01L21/76885H01L21/76895H01L21/823475H01L29/6659H01L27/11H01L27/1104H01L29/665H01L29/66583H01L21/823481H10B10/00H10B10/12
Inventor ABBOTT, TODD R.
Owner MICRON TECH INC