Data processing apparatus having memory protection unit

Abstract

A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to data processing systems. More particularly, this invention relates to data processing systems having memory protection units. [0003] 2. Description of the Prior Art [0004] It is known to control memory access in data processing systems using memory protection units. These memory protection units define a plurality of protection regions whose properties are configured by writing to protection unit registers. This provides a level of control over memory properties and enables different memory regions with different attributes to be specified. Memory protection units are similar to memory management units, but are simpler in the sense that they do not involve mapping of virtual to physical addresses. Furthermore, memory protection units do not use translation tables, but limit themselves to a relatively small number of regions in hardware to improve the predicatability of response. [0005] It i...

AI Technical Summary

Benefits of technology

[0011] The present technique recognises that allowing each memory region to be sub-divided into a plurality of individual sub-regions and providing in the memory region specifier associated with a memory region, a sub-region field for holding a sub-region membership value that specifies whether each of the sub-regions is a member sub-region, to which a defined set of memory attributes are applied or alternatively, a non-member sub-region to which the memory attributes associated with the memory region are not applied, provides a great deal of flexibility in the allocation of physical memory. The ability to associate a set of memory attributes to only specified portions of a memory region, that is individual sub-regions, allows the constraint whereby the starting address of a memory region must be an integer multiple of the memory region size to be overcome since, if it is desired to allocate a block of memory of a size for which it is not possible to define a whole memory region, it is still possible to allocate to that memory block a single memory region of a size larger than the required memory block but to specify as non-member sub-regions the portion of that larger memory region that is not required. The non-member sub-regions can then be utilised by other memory regions where they can be selected as member sub-regions.

[0026] It will be appreciated that the separate set of permutation logic could be provided to permute the sub-region membership value of each individual memory region. However, in an embodiment of the invention a single logic module is used to perform the permutation for each of the plurality of memory regions. This reduces the amount of circuitry required to manage the provision of the memory sub-regions.

Problems solved by technology

Furthermore, memory protection units do not use translation tables, but limit themselves to a relatively small number of regions in hardware to improve the predicatability of response.

However, in order to simplify the implementation cost there are usually certain constraints on the way that memory regions can be allocated.

This means that it is not possible in such systems to define memory regions of arbitrary size.

Although, systems having arbitrary sized memory regions can be built, it is much more expensive to do so.

Furthermore, the delineation of memory regions by known memory protection units is particularly inflexible in situations where application processes running on the data processing apparatus require access permission to different groups of peripheral devices.

This difficulty arises from the situation that typically a contiguous block of memory will be allocated to a full set of peripheral devices.

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