Pipelined analog to digital converter with capacitor mismatch compensation

a capacitor mismatch and converter technology, applied in the field of pipelined analog to digital converters, can solve the problems of reducing the number of comparators required, increasing the complexity of the circuit of flash analog-to-digital converters (“adc”), and requiring additional clock cycles to process the signal, so as to achieve the effect of not requiring excessive circuit complexity

US20070120725A1Active Publication Date: 2007-05-31HIMAX TECH LTD
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Publication Date
2007-05-31

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Abstract

In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.
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Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a pipelined analog to digital converter, especially to a pipelined analog to digital converter with a capacitor augmented and randomly selected as a feedback capacitor to compensate capacitance mismatch.

[0003] 2. Related Art of the Invention

[0004] Analog-to-digital conversion processes to convert an analog signal, which is most commonly represented as a voltage, into a digital format. Serial, delta-sigma, parallel, and pipelined methods are well known analog-to-digital conversion architectures. Different architectures are suited to different needs.

[0005] A serial analog-to-digital architecture offers a wide range of performance in analog-to-digital conversion, from low power and low resolution to quantizations with very high resolutions. A serial architecture typically quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution w...

Examples

Embodiment Construction

[0030] According to one aspect of the present invention, the present invention proposes a capacitor splitting approach to augment the capacitors with multiple numbers to, for example, double the capacitor numbers to address the problem of capacitor mismatch.

[0031]FIGS. 4A and 4B show schematic diagrams of a sub-converter in a 1.5-bit / stage pipelined ADC in a sampling phase and hold phase, respectively, according to a preferred embodiment of the present invention. With reference also to FIGS. 2A and 2B, in the sub-converter of the conventional 1.5-bit / stage pipelined ADC, there are two capacitors per stage. More particularly, the capacitor C1 is used as a feedback (FB) capacitor in a hold phase, and the capacitor C2 is used as an input connection capacitor in both the sampling and hold phases. According to a preferred embodiment of the present invention, at least one sub-converter stage in the pipelined ADC comprises capacitors with augmented numbers. The capacitors are augmented by...