Registration mark within an overlap of dopant regions

a registration mark and dopant technology, applied in the field of integrated circuit fabrication, can solve the problems of device out of specification, inoperable, and considerable cost consequences, and achieve the effect of enhancing the ability to perform subsequent fabrication steps

Inactive Publication Date: 2007-09-06
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This method improves the alignment of critical device layers, enhancing electrical operating parameters and simplifying subsequent fabrication steps by avoiding extra oxide fabrication, which ensures accurate and reliable device performance.

Problems solved by technology

A misalignment of a sequence of fabrication steps may mean that a device is out of specification or inoperable.
Yield and performance numbers for a device in production may vary significantly causing considerable cost consequences.

Method used

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  • Registration mark within an overlap of dopant regions
  • Registration mark within an overlap of dopant regions
  • Registration mark within an overlap of dopant regions

Examples

Experimental program
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Embodiment Construction

[0010] With reference to FIG. 1, an exemplary starting cross-section of a double well technology 100 begins with an oxide isolation layer 110 positioned on top of a semiconductor substrate 105. A continuous layer of silicon on insulator layer 115 is produced over the oxide isolation layer 110.

[0011] In a specific exemplary embodiment, the oxide isolation layer 110 ranges from 3,000 to 20,000 angstroms (Å) of silicon dioxide (SiO2). The oxide isolation layer 110 is, for example, thermally grown on top of the semiconductor substrate 105 if the substrate 105 is silicon. The silicon on insulator layer 115 is fabricated on top of the oxide isolation layer 110 to a thickness ranging from 0.2 to 20 micrometers (μm). The first oxide layer 120 is a 100 Å pad oxide thermally grown on the silicon on insulator layer 110. 200 Å of silicon nitride (SiN) is applied upon the first oxide layer 120 to form a silicon nitride layer 125. Upon the silicon nitride layer 125, a 500 Å layer of oxide is pro...

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Abstract

A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional application of pending U.S. patent application Ser. No. 11 / 217,250 filed Aug. 31, 2005.TECHNICAL FIELD [0002] The present invention relates to the general fabrication of an integrated circuit. More specifically, the invention is a registration mark for mask alignment and a method of fabrication of the mark in a semi-conductor technology. BACKGROUND ART [0003] In integrated circuit production, a layer-to-layer alignment and registration of fabrication masks is critical. The alignment of one mask layer to another or of a mask layer to a previously applied dopant is frequently critical to the fabrication of active devices or to electrical properties such as isolation capabilities, threshold parameters, or breakdown voltages. A misalignment of a sequence of fabrication steps may mean that a device is out of specification or inoperable. Yield and performance numbers for a device in production may vary significantly causin...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/76
CPCG03F7/70425G03F9/7076G03F7/70633
InventorDIETZ, FRANZDUDEK, VOLKERGRAF, MICHAELSCHWANTES, STEFANMILLER, GAYLE W. JR.
OwnerATMEL CORP