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Semiconductor wafer examination method and semiconductor chip manufacturing method

a semiconductor and wafer technology, applied in the direction of individual semiconductor device testing, semiconductor/solid-state device testing/measurement, instruments, etc., can solve the problems of failure of some semiconductor devices and semiconductor chips

Inactive Publication Date: 2007-11-01
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention provides a semiconductor wafer examination method and a semiconductor chip manufacturing method that can detect any possible failure at an earlier stage with high accuracy. This helps to screen out any defective wafers or chips, reducing the likelihood of failure and improving the reliability of the final product. The method includes steps of preparing the wafer, examining it with probing, pressing an electrode with a flat surface, and re-examining it with probing. The resulting semiconductor chip manufactured by this method is less likely to fail.

Problems solved by technology

This thus may cause a failure to some semiconductor devices of the semiconductor chips if heat and pressure act on the electrodes of the semiconductor chips in the subsequent process of semiconductor chip implementation, for example.

Method used

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  • Semiconductor wafer examination method and semiconductor chip manufacturing method
  • Semiconductor wafer examination method and semiconductor chip manufacturing method
  • Semiconductor wafer examination method and semiconductor chip manufacturing method

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Embodiment Construction

[0021] In the below, an exemplary embodiment of the invention is described by referring to the accompanying drawings. FIG. 1 is a diagram for illustrating a semiconductor wafer examination method of the embodiment. FIG. 2 is a cross sectional diagram schematically showing a process of the semiconductor wafer examination method. FIG. 3 is a schematic plan view of a wafer being an examination object. FIG. 4 is a schematic cross sectional view of a part of a chip area.

[0022] In the embodiment, a wafer is prepared for examination use. As shown in FIGS. 2 and 3, this wafer is configured by a semiconductor substrate 10 formed with a plurality of chip areas 12, which serve as semiconductor chips after wafer dicing. The chip areas 12 are provided with an integrated circuit that is not shown. The integrated circuit is not specifically defined by configuration, and may include an active element such as transistor or a passive element such as resistor, coil, or capacitor.

[0023] The chip area...

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Abstract

A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 11 / 458,781 filed on Jul. 20, 2006, which claims the benefit of Japanese Patent Application No.2005-214218, filed Jul. 25, 2005. The disclosures of the above applications are incorporated herein by reference.BACKGROUND [0002] 1. Technical Field [0003] The present invention relates to a semiconductor wafer examination method by wafer probing, and a semiconductor chip manufacturing method. [0004] 2. Related Art [0005] In the process of manufacturing a semiconductor chip, a semiconductor wafer formed with a plurality of semiconductor chips is subjected to an electric examination on a semiconductor chip basis so that screening is performed to find any defective piece. Such an examination includes a probe examination by probing. After the wafer is subjected to the probe examination, the wafer is generally diced so that chips are formed. This thus may cause a failure to some ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/66
CPCG01R31/287H01L22/20G01R31/2881G01R31/2875
Inventor YUZAWA, HIDEKIKIJIMA, KAZUHIRO
Owner SEIKO EPSON CORP
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