Compiler apparatus, compiler method, and compiler program

Inactive Publication Date: 2007-11-29
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]Therefore, the main object of the present invention is to provide a compiler apparatus which can convert a pro

Problems solved by technology

However, the effect of optimization is limited for local optimization of each basic block.
Thus, it i

Method used

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  • Compiler apparatus, compiler method, and compiler program
  • Compiler apparatus, compiler method, and compiler program
  • Compiler apparatus, compiler method, and compiler program

Examples

Experimental program
Comparison scheme
Effect test

embodiment

[0206]A compiler apparatus according to an embodiment of the present invention: reads a source program; performs word / phrase analysis to resolve the program into word / phrase strings; performs a syntax analysis for creating a syntax tree in a programming language based on the word / phrase strings; creates an intermediate program that is written with intermediate codes inside the apparatus based on the syntax tree created by the syntax analysis; performs optimization such as instruction scheduling for the intermediate program; and converts the intermediate program after allocation of resources such as registers are performed with respect to variables, into an execution format program.

[0207](Structure)

[0208]FIG. 1 is a functional block diagram showing the entire structure of a compiler apparatus A according to the embodiment of the present invention. The compiler apparatus A comprises a syntax analysis unit 1, an optimizing unit 2, a resource allocation unit 3, and an execution code gen...

operation example

[0262]Next, referring to FIG. 5, FIG. 9-FIG. 12, a specific example of the operation flow shown in FIG. 2 will be described exemplifying the case of a partial program that is a part of the source program F1 of FIG. 5A. It is assumed here that the intermediate code in this example is expressed with the intermediate code close to the source program F1.

[0263]In a step n11, the syntax analysis unit 1 performs the syntax analysis to the partial program in order to generate the partial intermediate code, and stores it in the inside the compiler apparatus A. Then, in the step n12, the program converting section 2A stores the hot path information F2 in the inside the program converting section 2A, upon receiving the input of the hot path information F2 where the path HP, that transits in order of the basic blocks B1, B2, B4, B5, B7 of the control flow graph, is made to be the hot path (see FIG. 5).

[0264]In the step n13, the optimizing unit 2 performs the control flow analysis and the datafl...

modification example 1

Acceptable Generation of Exception: See FIG. 14-FIG. 17

[0283]In the above-described embodiment, the intermediate code dependency analyzing part 2f generates dependency from the judgment intermediate code S203 to the exception generating intermediate code S102 in FIG. 12, so that an exception is not generated improperly. In Modification Example 1, however, such dependency is not generated. That is, the execution path intermediate code generating part 2b generates an intermediate code S401 anew as shown in a program of FIG. 14, and thereafter generates dependency from the intermediate code S401 to the exception generating intermediate code S102 as shown in a program of FIG. 15.

[0284]That is, the execution path intermediate code generating part 2b inserts the variable and the code to the head of the execution path intermediate code string which are generated as below.[0285]Generate a return point holding variable that is a special variable for holding the returning address in returning...

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Abstract

A high-sped block is formed by generating and connecting a new basic block (contains an intermediate code obtained by performing variable replacing processing to a path replacement target variable of the intermediate code on a hot path of an original partial program and contains a branching intermediate code where a branching instruction on the hot path is converted so as to execute the hot path), and a basic block with an intermediate code for restoring value of path guarantee variable among the path replacement target variables to a value of an original variable. When an execution result of a conditional branching intermediate code is true, the speeding up of the original program is achieved through executing the basic block, and performing dependency analysis and dependency generation between the intermediate codes in the high-speed block and scheduling of the instructions.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a compiler apparatus, a compiler method, and a compiler program. More specifically, the present invention relates to a technique for achieving optimized compiling in terms of the execution speed.[0003]2. Description of the Related Art[0004]Conventionally, a compiler apparatus, that performs optimization to reduce the execution time of a program, is used in order to improve the performance of the program that is loaded on a computer system for processing a vast amount of data.[0005]In the compiler apparatus, instruction scheduling for rearranging the order of instructions is used so as to improve the execution efficiency of the program in order to perform optimization. Further, in performing optimization, the compiler apparatus divides the program by a basic block unit through control flow analysis focusing attention on the instruction sentence at a branching point of the program and the ...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/4441
Inventor TANAKA, AKIRAHATANO, FUMIHIROYAMANA, TOMOHIROMINEO, MASAAKI
Owner PANASONIC CORP
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