Apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device
a multi-processor device and failure analysis technology, applied in the field of improved, can solve the problems of significant drawbacks to known fault detection by duplication mechanisms, add to the total cost of manufacturing the integrated circuit chip, and make fault detection much more time-consuming and labor-intensiv
Inactive Publication Date: 2007-12-27
IBM CORP
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Benefits of technology
[0016]In one illustrative embodiment, the multiprocessor SoC may be a heterogeneous multiprocessor SoC, such as the Cell Broadband Engine (CBE), also known as the Broadband Processor Architecture, available from International Business Machines, Inc. of Armonk, N.Y. In such a heterogeneous multiprocessor SoC, a control processor is provided along with a plurality of co-processors which may operate using a different instruction set from that of the control processor. The mechanisms of the illustrative embodiments may make use of an existing debug bus provided in the heterogeneous multiprocessor SoC for performing the transfer of signals from the co-processors to an existing TLA in the heterogeneous multiprocessor SoC. Logic may be provided in each of the co-processors for facilitating the comparisons between co-processors as the modules described above. In this way, faulty co-processors may be identified using on-chip internal signal tracing and comparison between duplicate co-processors.
Problems solved by technology
The time required to test such modules significantly adds to the total cost of manufacturing the integrated circuit chip.
While these test methods are necessary for exhaustive testing of the integrated circuit device, they are time consuming processes that require external test equipment to extract test results from the integrated circuit chip and perform the necessary analysis for determining if the integrated circuit chip is operating properly.
There are significant drawbacks to known fault detection by duplication mechanisms.
For example, in addition to the overhead of having to provide a duplicate module, fault detection by duplication requires an external comparator (external to the integrated circuit chip) for comparing the outputs of the module under test and the duplicate module.
In addition, such fault detection is not able to monitor important internal signals for comparison, making fault detection much more time consuming.
If there is a discrepancy, then a faulty module may be present.
The integrated circuit device may then be identified as faulty if a discrepancy between the internal signals is detected by the comparison.
Method used
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[0034]The illustrative embodiments provide an apparatus and method for accelerating test, debug, and failure analysis of a multiprocessor system. As such, the mechanisms of the illustrative embodiments may be applied to any multiprocessor system that has modules that are duplicates of one another, i.e. modules that have the same configuration, barring any manufacturing discrepancies. Fault detection is performed using fault detection by duplication on internal signals of these modules and on-chip logic for performing comparisons and analysis of the results of such comparisons.
[0035]One multiprocessor system in which the mechanisms of the illustrative embodiments may be implemented is the Cell Broadband Engine (CBE) available from International Business Machines, Inc. The CBE is a multi-core processor comprising a control processor and multiple identical copies of co-processors, barring any manufacturing discrepancies. These co-processors are referred to as Synergistic Processing Ele...
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An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
Description
BACKGROUND[0001]1. Technical Field[0002]The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to an apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device.[0003]2. Description of Related Art[0004]When manufacturing integrated circuit chips, it is important to be able to test the operation of the modules, e.g., processors, on the integrated circuit chips in order to ensure their proper operation. The time required to test such modules significantly adds to the total cost of manufacturing the integrated circuit chip. Thus, if it is possible to improve upon the test time, the cost of manufacturing integrated circuit chips may be reduced. Moreover, efficient debug and failure analysis of such modules helps in reducing the total time to market as well as increases the yield, resulting in overall reduction in cost of manufacturing the integrated circuit c...
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Login to View More IPC IPC(8): G01R31/28G06F11/00
CPCG06F11/2236
InventorDATTA, RAMYANSHUFERNSLER, MATTHEW E.HOFSTEE, HARM P.
OwnerIBM CORP