Semiconductor Device with Reduced Capacitance Tolerance Value
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second embodiment
[0029]FIG. 3A schematically shows the layer structure of the invention, in accordance with the schematic circuit diagram of FIG. 3B. This latter figure shows a parallel connection of a first capacitor C1′, a second capacitor C2′, and a third, and fourth capacitor C3.1 and C3.2, together forming an overall capacitance C as a function-determining capacitance C of a semiconductor device (not shown). Deviating from FIGS. 2A to 2E, FIG. 3A shows a surface portion of a semiconductor substrate 13, as well as an MOS structure provided thereon, i.e., a structure formed in a FEOL process, in addition to a BEOL structure provided thereon.
[0030]A P well 14 is provided in the surface of the semiconductor substrate 13, p+ doped regions 15.1, 15.2 are provided with a predetermined distance from each other within the P well 14. On the main surface of the semiconductor substrate 13, bridging the distance between the p+ regions 15.1, 15.2, an oxide layer 16 comprising side wall spacers 16.1, 16.2 is ...
first embodiment
[0033]Like the first embodiment, the formation of the respective capacitor elements, including the sandwich capacitor C2′ and the MOS capacitors C3.1 and C3.2, is basically conventional and, therefore no detailed description in this regard is necessary. However, an adequate connection is essential between the several structures or capacitor elements, respectively, by means of specifically arranged vias, to provide for the intended parallel connection of the various partial capacitances C1′, C2′, C3.1, and C3.2 of the total capacitance C.
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