Lithographic alignment marks

Abstract

Precise and repeatable alignment performance using asymmetric illumination is achieved by properly structuring, as by segmenting, an alignment mark on a reticle of a photolithographic exposure apparatus as a function of the type of asymmetric illumination, thereby improving resolution and repeatability of an alignment mark formed on a target substrate. Embodiments include double exposure techniques using dipole illumination with an angularly segmented alignment mark, e.g., at 45°, such that the first-order diffracted light is sent at 45° from the initial position of the dipole illumination.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to lithographic exposure tools and their use in fabricating semiconductor devices with improved and repeatable alignment performance. The present invention is particularly applicable in fabricating semiconductor devices with dimensions in the deep sub-micron range using aggressive illumination techniques.BACKGROUND ART[0002]It is well recognized that the formation of electrical elements within an integrated circuit at smaller sizes and increased densities provides benefits in both performance and functionality. However, as the dimensions of semiconductor device features continue to shrink into the deep sub-micron range, process control windows shrink commensurately. The minimum feature size depends on the chemical and optical limits of a particular lithographic system, and the tolerance for distortions of the shape. Smaller design rules necessitate more accurate and repeatable overlay metrology to ensure adequate le...

AI Technical Summary

Benefits of technology

[0006]An advantage of the present invention is a photolithic exposure apparatus for fabricating semiconductor devices having ultrafine dimensions using aggressive or off-axis illumination with precise and repeatable alignment.

[0007]Another advantage of the present invention is a method of fabricating a semiconductor device having dimensions in the deep sub-micron range using aggressive or off-axis illumination techniques with precise and repeatable alignment.

[0008]Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.

[0009]According to the present invention, the foregoing and other advantages are achieved in part by a photolithographic exposure apparatus comprising: an illumination source for emitting a type of illumination; and a reticle having a reticle alignment mark thereon, the reticle alignment mark being structured depending on the type of illumination such that resolution of a substrate alignment mark on a substrate is enhanced, thereby avoiding degradation of alignment quality in a direction that would otherwise occur using the type of illumination, wherein the substrate alignment mark is different from the reticle alignment mark.

[0010]Embodiments include photolithographic exposure apparatuses comprising dipole, quadrupole, multipole, and annular illumination sources. Further embodiments include photolithographic exposure apparatuses containing a dipole illumination source and a reticle having a first segmented alignment mark, such as an alignment mark comprising segments angled at about 40° to about 50°, e.g., to about 43° to about 47°.

[0011]Another advantage of the present invention is a method of fabricating a semiconductor device the method comprising: positioning a substrate in a photolithographic exposure apparatus comprising: an illumination source for emitting a type of illumination; and a reticle having a first reticle alignment mark thereon, the first reticle alignment mark being structured depending on the type of illumination such that resolution of a substrate alignment mark to be formed on the substrate is enhanced, thereby avoiding directional alignment degradation that would otherwise occur using the type of illumination, wherein the first reticle alignment mark is different from the substrate alignment mark; and forming a first pattern, including the substrate alignment mark, on the substrate using the first reticle.

Problems solved by technology

However, as the dimensions of semiconductor device features continue to shrink into the deep sub-micron range, process control windows shrink commensurately.

In addition to the limitations of conventional lithography, the manufacturing cost attendant upon accurately forming ultrafine design features increase, thereby requiring advances in tool design and processing design for efficient use of facilities and high manufacturing throughput.

However, the end points of lines, such as alignment marks, are not as well defined and / or as easily detectable.

However, these techniques have not been completely successful and suffer from low manufacturing throughput, some techniques requiring the repeated use of several tools.

Further, in attempting to apply aggressive, off-axis illumination techniques in combination with double exposure techniques, alignment difficulties are greatly exacerbated due to the need to align successive resist patterns.

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