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Input/output circuit

Inactive Publication Date: 2011-03-31
SEMICON COMPONENTS IND LLC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]The preferred embodiments of the present invention have been developed in view of the above-mentioned and / or other problems in the related art. The preferred embodiments of the present invention can significantly improve upon existing methods and / or apparatuses.
[0013]Among other potential advantages, some embodiments can provide a signal I / O circuit low in power consumption or capable of minimizing power consumption.

Problems solved by technology

This constant electric flow flowing through the comparator causes a large amount of power consumption.

Method used

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Embodiment Construction

[0026]In the following paragraphs, some preferred embodiments of the present invention will be described by way of example and not limitation. It should be understood based on this disclosure that various other modifications can be made by those in the art based on these illustrated embodiments.

[0027]Hereinafter, some preferable embodiments of the present invention will be explained with reference to the attached drawings.

[0028]FIG. 1 is a schematic structural view of a signal input / output circuit (I / O circuit) according to an embodiment of the present invention. In FIG. 1, the reference numeral “1” denotes a transmitter, “2” denotes a coupling capacitance, “5” denotes a data processing portion, “8” denotes a transmitting portion, “10” denotes a control circuit, and “31” denotes a receiving portion.

[0029]The receiving portion 31 includes an H-level detector 6 and an L-level detector 7. The H-level detector 6 is a detector configured to detect a change of the signal level of the inpu...

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Abstract

In some embodiments, an input / output (I / O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I / O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.

Description

[0001]This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2009-224992 filed on Sep. 29, 2009, the entire disclosure of which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]Some preferred embodiments of the present invention relate to an input / output circuit (I / O circuit), and, more specifically to a communication I / O interface capable of reducing power consumption.[0004]2. Description of the Related Art[0005]The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.[0006]In recent years, considering environments, electronic products are required to be operated at a low power consumption rate. In a capacity-coupled type communication device commonly used in a signal I / O circuit arranged between ICs mounted in an electronic product, the power consumption can be roughly...

Claims

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Application Information

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IPC IPC(8): H03K17/687H03K17/00
CPCG06F1/3253Y02B60/1235G06F13/4072Y02D10/00
Inventor YAMADA, SUSUMU
Owner SEMICON COMPONENTS IND LLC