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Circuit providing load isolation and memory domain translation for memory module

a memory module and circuit technology, applied in the field of memory modules of computer systems, can solve the problems of imposing limitations on the size of memory arrays of memory modules, limited memory density that can be incorporated in each memory slot,

Active Publication Date: 2011-04-14
NETLIST INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This solution enhances memory density and performance by reducing the load on the system, allowing for faster operation and increased memory capacity without sacrificing signal integrity, and enables the use of lower-cost, lower-density memory devices to achieve higher-density configurations.

Problems solved by technology

By only supporting one-rank and two-rank memory modules, the memory density that can be incorporated in each memory slot is limited.
Various aspects of the design of a memory module impose limitations on the size of the memory arrays of the memory module.

Method used

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  • Circuit providing load isolation and memory domain translation for memory module
  • Circuit providing load isolation and memory domain translation for memory module
  • Circuit providing load isolation and memory domain translation for memory module

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0059]

/ / =========================== declarations regrasN_R, casN_R, weN_R; wireactv_cmd_R, pch_cmd_R, pch_all_cmd_R, ap_xfr_cmd_R_R; wirexfr_cmd_R,mrs_cmd,rd_cmd_R; / / - - - - - - - - - - - - - - - - - - - - - - - - - DDR 2 FET regbrs0N_R; / / registered chip sel regbrs1N_R; / / registered chip sel regbrs2N_R; / / registered chip sel regbrs3N_R; / / registered chip sel wiresel; wiresel_01; wiresel_23; wirerd_R1; wirewr_cmd_R,wr_R1; regrd_R2,rd_R3,rd_R4,rd_R5; regwr_R2,wr_R3,wr_R4,wr_R5; regenfet1,enfet2,enfet3,enfet4,enfet5,enfet6; wirewr_01_R1,wr_23_R1; regwr_01_R2,wr_01_R3,wr_01_R4; regwr_23_R2,wr_23_R3,wr_23_R4; wirerodt0_a,rodt0_b; / / =========================== logic always @(posedge clk_in)beginbrs0N_R brs1N_R brs2N_R brs3N_R rasN_R casN_R weN_R endassign sel = ~brs0N_R | ~brs1N_R | ~brs2N_R | ~brs3N_R ;assign sel_01 = ~brs0N_R | ~brs1N_R ;assign sel_23 = ~brs2N_R | ~brs3N_R ;assign actv_cmd_R = !rasN_R & casN_R & weN_R; / / activate cmdassign pch_cmd_R = !rasN_R & casN_R & !weN_R ; / / pc...

example 2

[0131]

always @(posedge clk_in)beginrs0N_R rasN_R casN_R weN_R end / / Gated Chip Selectsassignpcs0a_1 = (~rs0_in_N & ~ras_in_N & ~cas_in_N) / / ref,md reg set| (~rs0_in_N & ras_in_N & cas_in_N) / / ref exit, pwr dn| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & a10_in) / / pchg all| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & ~a10_in & ~ba2_in) / / pchg single bnk| (~rs0_in_N & ~ras_in_N & cas_in_N & we_in_N   & ~ba2_in) / / activate| (~rs0_in_N & ras_in_N & ~cas_in_N    & ~ba2_in) / / xfr;assignpcs0b_1 = (~rs0_in_N & ~ras_in_N & ~cas_in_N) / / ref,md reg set| (~rs0_in_N & ras_in_N & cas_in_N) / / ref, exit, pwr dn| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & a10_in) / / pchg all| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & ~a10_in & ba2_in) / / pchg single bnk| (~rs0_in_N & ~ras_in_N & cas_in_N & we_in_N   & ba2_in) / / activate| (~rs0_in_N & ras_in_N & ~cas_in_N    & ba2_in) / / xfr / / --------------------------------------- always @(posedge clk_in)begina4_r a5_r a6_r a10_r ba0_r ba1_r ba2_r q_mrs...

example 3

[0133]

/ / latched a13 flags cs0, banks 0-3 always @(posedge clk_in)  if (actv_cmd_R & ~rs0N_R & ~bnk1_R & ~bnk0_R ) / / activate  begin l_a13_00   end always @(posedge clk_in)  if (actv_cmd_R & ~rs0N_R & ~bnk1_R & bnk0_R) / / activate  begin l_a13_01   end always @(posedge clk_in)  if (actv_cmd_R & ~rs0N_R & bnk1_R & ~bnk0_R) / / activate  begin l_a13_10   end always @(posedge clk_in)  if (actv_cmd_R & ~rs0N_R & bnk1_R & bnk0_R) / / activate  begin l_a13_11   end / / gated casassign cas_i = ~(casN_R);assign  cas0_o = ( ~rasN_R & cas_i)| ( rasN_R & ~l_a13_00 & ~bnk1_R & ~bnk0_R & cas_i)| ( rasN_R & ~l_a13_01 & ~bnk1_R & bnk0_R & cas_i)| ( rasN_R & ~l_a13_10 & bnk1_R & ~bnk0_R & cas_i)| ( rasN_R & ~l_a13_11 & bnk1_R & bnk0_R & cas_i);assign  cas1_o = ( ~rasN_R & cas_i)| ( rasN_R & l_a13_00   & ~bnk1_R & ~bnk0_R & cas_i)| ( rasN_R & l_a13_01   & ~bnk1_R & bnk0_R & cas_i)| ( rasN_R & l_a13_10   & bnk1_R & ~bnk0_R & cas_i)| ( rasN_R & l_a13_11   & bnk1_R & bnk0_R & cas_i);assignpcas_0_N = ~cas0_o;a...

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Abstract

A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row / column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is a continuation of U.S. patent application Ser. No. 12 / 629,827, filed Dec. 2, 2009, which is a continuation of U.S. patent application Ser. No. 12 / 408,652, filed Mar. 20, 2009, which is a continuation of U.S. patent application Ser. No. 11 / 335,875, filed Jan. 19, 2006, which claims the benefit of U.S. Provisional Appl. No. 60 / 645,087, filed Jan. 19, 2005 and which is a continuation-in-part of U.S. patent application Ser. No. 11 / 173,175, filed Jul. 1, 2005, which claims the benefit of U.S. Provisional Appl. No. 60 / 588,244, filed Jul. 15, 2004 and which is a continuation-in-part of U.S. patent application Ser. No. 11 / 075,395, filed Mar. 7, 2005, which claims the benefit of U.S. Provisional Appl. No. 60 / 550,668, filed Mar. 5, 2004, U.S. Provisional Appl. No. 60 / 575,595, filed May 28, 2004, and U.S. Provisional Appl. No. 60 / 590,038, filed Jul. 21, 2004. U.S. patent application Ser. Nos. 12 / 629,827, 12 / 408,652, 11 / 335...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C8/16G11C8/06G11C8/18
CPCG11C5/04G06F12/00G06F13/00G06F13/1673G06F13/4243G06F13/4282Y02D10/00G11C7/1072G11C15/00
Inventor SOLOMON, JEFFREY C.BHAKTA, JAYESH R.
Owner NETLIST INC