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Semiconductor device and method of manufacturing the same

a technology of semiconductor devices and semiconductors, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of deterioration of control gate electrodes, increased agglomeration, and more difficult control of the diffusion length of metallic atoms

Inactive Publication Date: 2011-11-10
ENDO MASATO +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach ensures consistent resistance values across memory cells, reduces the progression of control gate electrode deterioration, and maintains performance even with high aspect ratios, enhancing the reliability of semiconductor storage devices.

Problems solved by technology

However, in general, the deeper the region of the polysilicon film desired to be turned into the metallic silicide becomes in the depth direction of the polysilicon film, the more difficult control of the diffusion length of the metallic atoms becomes.
As a result, an increase in the resistance value of a control gate electrode, an increase in the variation in the resistance value of a control gate electrode among cells, progress in deterioration of a control gate electrode caused by an increase in agglomeration, and the like described above occur.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

Experimental program
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first embodiment

[0034]A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2A, 2B, 2C to 14A, 14B, and 14C. FIG. 1 is a plan view showing a part of the semiconductor device according to the first embodiment of the present invention. FIGS. 2A to 2C are cross-sectional views schematically showing a main part of the semiconductor device according to the first embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views taken along lines IIA-IIA and IIB-IIB, respectively. FIG. 2C is a cross-sectional view of a transistor (peripheral transistor) in a peripheral circuit region.

[0035]As shown in FIG. 1, the semiconductor device has selection gate (selection gate transistor) regions and memory cell (memory cell transistor) regions. The memory cell region is interposed between selection gate regions. An element isolation insulating film 1 of a shallow trench isolation (STI) structure is formed on a semiconductor ...

second embodiment

[0105]A second embodiment differs from the first embodiment in the step of exposing a second part 3b of a control gate electrode.

[0106]A semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 15B to 18A, and 18B. FIG. 15A is a cross-sectional view taken along line IIB-IIB in FIG. 1, and is a cross-sectional view in the same position as FIG. 2B of the first embodiment. FIG. 15B is a cross-sectional view of a peripheral transistor, and is a cross-sectional view in the same position as FIG. 2C of the first embodiment. The cross-sectional view taken along line IIA-IIA in FIG. 1 is the same as that of the first embodiment (FIG. 2A).

[0107]As shown in FIGS. 15A and 15B, the entire side surface on the opposite side of the cell transistor of the stacked gate electrode structure of the selection gate transistor is covered with a barrier film 25. The entire side surface of the stacked gate electrode structure of the peri...

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Abstract

A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source / drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source / drain regions formed on the surface of the semiconductor substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of and claims the benefit under 35 U.S.C. §120 from U.S. application Ser. No. 11 / 854,814, filed Sep. 13, 2007, which claims priority under 35 U.S.C. §119 from Japanese Application No. 2006-251599, filed Sep. 15, 2006, the entire contents of each of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to, for example, a stacked transistor having a structure in which a floating gate electrode and a control gate electrode are provided through an inter-electrode insulating film and a method of manufacturing the same.[0004]2. Description of the Related Art[0005]A nonvolatile semiconductor storage device using a transistor having a structure in which a floating gate electrode, an inter-electrode insulating film, and a control gate electrode...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/115H10B69/00
CPCH01L27/105H01L27/11529H01L27/11526H10B41/40H10B41/41H01L21/28052H01L21/3213
Inventor ENDO, MASATOARAI, FUMITAKA
Owner ENDO MASATO