Semiconductor device reducing risks of a wire short-circuit and a wire flow

Abstract

A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

Description

[0001]This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-174576, filed on Aug. 10, 2011, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a semiconductor device, and more particularly to a multi-chip package type semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate.[0004]2. Description of Related Art[0005]Various multi-chip package type semiconductor devices are already known.[0006]By way of illustration, JP-A 2002-110898 (which will be also called Patent Document 1 and which corresponds to U.S. Pat. No. 7,115,977) discloses a semiconductor device comprising a substrate having a surface on which a wiring pattern is formed; a first semiconductor element (a first semiconductor chip), mounted on the substrate, having first electrode pads; a second semiconductor element ...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device with a wiring substrate and two semiconductor chips connected through wires. The first semiconductor chip has larger electrode pads than the second semiconductor chip, while the second wires have wider parts at their first ends to connect to the second electrode pads. The second wires also have bump electrodes smaller than the second electrode pads to provide better connection. This structure allows for efficient wiring and minimizes signal loss, improving the overall performance of the semiconductor device.

Problems solved by technology

However, the semiconductor device disclosed in Patent Document 1 involves problems as follows.

In this event, there is a fear that bonding cannot be favorably carried out to smaller electrode pads if wires having large diameters suited to large electrode pads are used.

If wires having small diameters suited to small electrode pads are used, the wires become easily deformed on molding, and a wire short-circuit of a wire flow have become increasingly risky.

Accordingly, there is a limit to connect the wide width parts of the wires with the electrode pads which have small pad sizes and which are arranged at a narrow pitch and there still remains the risk of the wire short-circuit due to flow of resin on molding.

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